Inventor
GILDA GLENN DAVID
US14 patents
Patents
14 patentsUS6920519B1Jul 19, 2005
System and method for supporting access to multiple I/O hub nodes in a host bridge
IBM81 citations96
US6115795ASep 5, 2000
Method and apparatus for configurable multiple level cache with coherency in a multiprocessor system
IBM44 citations95
US6490660B1Dec 3, 2002
Method and apparatus for a configurable multiple level cache with coherency in a multiprocessor system
IBM19 citations92
US6065101AMay 16, 2000
Pipelined snooping of multiple L1 cache lines
IBM41 citations92
US6785759B1Aug 31, 2004
System and method for sharing I/O address translation caching across multiple host bridges
IBM24 citations91
US6438657B1Aug 20, 2002
Pipelined snooping of multiple L1 cache lines
IBM12 citations73
US11449397B2Sep 20, 2022
Cache array macro micro-masking
IBM2 citations72
US11200119B2Dec 14, 2021
Low latency availability in degraded redundant array of independent memory
IBM4 citations72
US11646861B2May 9, 2023
Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes
IBM2 citations69
US6138206AOct 24, 2000
Data register for multicycle data cache read
IBM15 citations66
US11520659B2Dec 6, 2022
Refresh-hiding memory system staggered refresh
IBM0 citations62
US11609817B2Mar 21, 2023
Low latency availability in degraded redundant array of independent memory
IBM0 citations61
US11907074B2Feb 20, 2024
Low-latency deserializer having fine granularity and defective-lane compensation
IBM0 citations60
US11960426B2Apr 16, 2024
Cable pair concurrent servicing
IBM0 citations47