Inventor

ROTH RON M

IL41 patents

⚠️ This page may combine multiple inventors who share the name “ROTH RON M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROTH RON M

HEWLETT PACKARD ENTPR DEV LP

Fault-tolerant dot product engine

Storing run-length limited two-dimensional encoded bit patterns in memory arrays

Bit-flip coding

Gray encoding for analog content addressable memory in general computing

On-access error correction for content-addressable memory

Error-detection schemes for analog content-addressable memories

Fault-tolerant dot product engine

Inequality check with ternary cam

Compact CAM array for decision tree inference (tree-CAM)

Increased precision analog content addressable memories

Constant hamming weight coding

Data storing in memory arrays

List decode circuits

ORDENTLICH ERIK

Antipodal-mapping-based encoders and decoders

Systems and methods for encoding information for storage in an electronic memory and for decoding encoded information retrieved from an electronic memory

Memory array including multi-state memory devices

Method and system for encoding data for storage in a memory array

Coding for crossbar architecture

Approximate enumerative coding method and apparatus

Overwriting a memory array

Minimized half-select current in multi-state memories

Encoding data based on weight constraints

HEWLETT PACKARD CO

Error correction method and apparatus based on two-dimensional code array with reduced redundancy

Method and apparatus having cascaded decoding for multiple runlength-limited channel codes

Apparatus and method for efficient arithmetic in finite fields through alternative representation

Two-dimensional DC-free encoder and decoder

Method of generating address configurations for solid state memory

Method and apparatus for generating runlength-limited coding with DC control

Burst error and additional random bit error correction in a memory

Apparatus and method for efficient arithmetic in finite fields through alternative representation

Fault-tolerant neighborhood-disjoint address logic for solid state memory

HEWLETT PACKARD DEVELOPMENT CO

Error detection and correction in a layered, 3-dimensional storage architecture

Constant-weight-code-based addressing of nanoscale and mixed microscale/nanoscale arrays

Inline fuses in programmable crossbar arrays

Data storage in memory array with less than half of cells in any row and column in low-resistance states

Memory controller using crisscross error-correcting codes

Defect-tolerant demultiplexers based on threshold logic

IBM

Method and means for coding and rebuilding that data contents of unavailable DASDs or rebuilding the contents of DASDs in error in the presence of reduced number of unavailable DASDs in a DASD array

AGILENT TECHNOLOGIES INC

Partitioning of polymorphic DNAs

BREMLER-BARR ANAT

Efficient detection of errors in associative memory

(unassigned)

Fault-tolerant address logic for solid state memory