Inventor

LU YUNG-CHENG

US145 patents

⚠️ This page may combine multiple inventors who share the name “LU YUNG-CHENG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LU YUNG-CHENG

APPLIED MATERIALS INC

Method of decreasing the K value in SiOC layer deposited by chemical vapor deposition

Plasma processes for depositing low dielectric constant films

Method of depositing low k films using an oxidizing plasma

Plasma processes for depositing low dielectric constant films

Plasma processes for depositing low dielectric constant films

Plasma processes for depositing low dielectric constant films

Plasma processes for depositing low dielectric constant films

Plasma processes for depositing low dielectric constant films

Method of improving moisture resistance of low dielectric constant films

Plasma processes for depositing low dielectric constant films

Method of improving moisture resistance of low dielectric constant films

Low dielectric constant film produced from silicon compounds comprising silicon-carbon bonds

Plasma processes for depositing low dielectric constant films

Method of improving moisture resistance of low dielectric constant films

Plasma processes for depositing low dielectric constant films

Method of depositing low k films

Plasma processes for depositing low dielectric constant films

Method of depositing low K films

Method of decreasing the K value in SIOC layer deposited by chemical vapor deposition

Method of depositing low dielectric constant carbon doped silicon oxide

Method of decreasing the k value in sioc layer deposited by chemical vapor deposition

TAIWAN SEMICONDUCTOR MFG

Method for forming low dielectric constant damascene structure while employing carbon doped silicon oxide planarizing stop layer

Interconnect structure for semiconductor devices

Semiconductor device and fabrication method thereof

Post-ESL porogen burn-out for copper ELK integration

Insulating layer having graded densification

Method for forming a capping layer over a low-k dielectric with improved adhesion and reduced dielectric constant

Semiconductor device and method of forming vertical structure

Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio

Interconnects with harmonized stress and methods for fabricating the same

Method for forming a multi-layer low-K dual damascene

Process for improving dielectric properties in low-k organosilicate dielectric material

Method of forming copper interconnects

Integration film scheme for copper / low-k interconnect

Synergy effect of alloying materials in interconnect structures

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device and method

Dielectric spacer to prevent contacting shorting

Method for operating a polishing head and method for polishing a substrate

Multi-layer mask and method of forming same

Platen assembly, chemical-mechanical polisher, and method for polishing substrate

Barc-assisted process for planar recessing or removing of variable-height layers

Replacement gate process for semiconductor devices

Nanosheet field-effect transistor device and method of forming

Semiconductor device and method of manufacture

Post-formation mends of dielectric features

Semiconductor device and method

Semiconductor device and method of manufacture

Dielectric spacer to prevent contacting shorting

Post-formation mends of dielectric features

YU CHEN-HUA

Interconnect structure having a silicide/germanide cap layer