Inventor

BEINTNER JOCHEN

US63 patents

⚠️ This page may combine multiple inventors who share the name “BEINTNER JOCHEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BEINTNER JOCHEN

IBM

Vertical Fin-FET MOS devices

Process for fabrication of FinFETs

Dual gate FinFet

Device fabrication by anisotropic wet etch

Structure and method of making double-gated self-aligned finFET having gates of different lengths

Dense chevron finFET and method of manufacturing same

Dual function FinFET, finmemory and method of manufacture

Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI structure with elevated source/drain

Nitrided STI liner oxide for reduced corner device impact on vertical device performance

Trench isolation processes using polysilicon-assisted fill

Pitcher-shaped active area for field effect transistor and method of forming same

Removable inorganic anti-reflection coating process

Raised STI process for multiple gate ox and sidewall protection on strained Si/SGOI sructure with elevated source/drain

Structure and methods for process integration in vertical DRAM cell fabrication

Formation of self-aligned buried strap connector

Method for fabricating integrated circuit features

Structure and methods for process integration in vertical DRAM cell fabrication

Self-aligned buried strap process using doped HDP oxide

Self-aligned near surface strap for high density trench DRAMS

Pitcher-shaped active area for field effect transistor and method of forming same

Structure and method of forming a notched gate field effect transistor

Method and device for array threshold voltage control by trapped charge in trench isolation

Method of forming a collar using selective SiGe/Amorphous Si Etch

Device fabrication by anisotropic wet etch

Corner clipping for field effect devices

Structure and method for ultra-small grain size polysilicon

Self-aligned buried strap process using doped HDP oxide

INFINEON TECHNOLOGIES CORP

Formation of controlled trench top isolation layers for vertical transistors

Field effect transistor and method of fabrication

Dynamic random access memory

Formation of controlled trench top isolation layers for vertical transistors

Silicon nitride island formation for increased capacitance

Method for manufacturing memory cell with trench capacitor

Self aligned channel implantation

Field effect transistor and method of fabrication

INFINEON TECHNOLOGIES AG

Nitrogen implantation using a shadow effect to control gate oxide thickness in DRAM semiconductor

Integrated spacer for gate/source/drain isolation in a vertical array structure

Trench isolation employing a high aspect ratio trench

Trench capacitor with buried strap

Collar formation by selective oxide deposition

Low temperature self-aligned collar formation

Spacer formation process using oxide shield

Process integration for integrated circuits

SIEMENS AG

Memory cell structure and fabrication

Buffer layer for improving control of layer thickness

Method for fabricating transistors

Memory cell structure and fabrication

Method for forming electrical isolation for semiconductor devices

BOSCH GMBH ROBERT

Micromechanical sensor that includes a stress decoupling structure

QIMONDA AG

Method of implanting using a shadow effect