Inventor

MATHEW SURAJ J

US21 patents

⚠️ This page may combine multiple inventors who share the name “MATHEW SURAJ J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MATHEW SURAJ J

MICRON TECHNOLOGY INC

Memory cells and memory arrays

Memory cells and memory arrays

Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith

Memory cells and memory arrays

Integrated assemblies having spacers of low permittivity along digit-lines, and methods of forming integrated assemblies

Memory cells and memory arrays

Memory cells and memory arrays

Method to fabricate surface p-channel CMOS

Sacrificial deposition layer as screening material for implants into a wafer during the manufacture of a semiconductor device

Vertical two-transistor single capacitor memory cells and memory arrays

Memory cells and memory arrays

Methods of forming a vertical transistor, methods of forming memory cells, and methods of forming arrays of memory cells

Methods of forming a vertical transistor

Transistors having argon gate implants and methods of forming the same

Method to fabricate surface p-channel CMOS

Memory cells and memory arrays

MATHEW SURAJ J

High density thyristor random access memory device and method

High density thyristor random access memory device and method

PAREKH KUNAL R

Methods of forming recessed access devices associated with semiconductor constructions

GUHA JAYDIP

Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith

KARDA KAMAL M

Memory cells having capacitor dielectric directly against a transistor source/drain region