Inventor

LASSERRE SERGE

FR49 patents

⚠️ This page may combine multiple inventors who share the name “LASSERRE SERGE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LASSERRE SERGE

TEXAS INSTRUMENTS INC

Audio and video decoder circuit and system

Multiple microprocessors with a shared cache

Software controlled cache configuration based on average miss rate

Unified memory management system for multi processor heterogeneous architecture

Traffic controller using priority and burst control for reducing access latency

Memory control using memory state information for reducing access latency

Real time window address calculation for on-screen display

Transport stream packet parser system

Using IMPDEP2 for system commands related to Java accelerator hardware

Fault management and recovery based on task-ID

Cache and DMA with a global valid bit

Interruptible and re-entrant cache clean range instruction

MMU descriptor having big/little endian bit to control the transfer data between devices

Cache with DMA and dirty bits

Level 2 smartcache architecture supporting simultaneous multiprocessor accesses

Master/slave processing system with shared translation lookaside buffer

Cache with block prefetch and DMA

Task based priority arbitration

Cache/smartcache with interruptible block prefetch

Smart cache

Inter-processor control

Processing system with shared translation lookaside buffer

Energy-aware scheduling of application execution

Data transfer controlled by task attributes

Memory allocation in a multi-processor system

Cache with multiple fill modes

Data processing apparatus, system and method

Cache operation based on range of addresses

Traffic controller using priority and burst control for reducing access latency

Optimized hardware cleaning function for VIVT data cache

Digital signal processor with direct and virtual addressing

Computer circuits, systems, and methods using partial cache cleaning

Management of stack-based memory usage in a processor

Stack register reference control bit in source operand of instruction

Synchronizing stack storage

Processor with a split stack

Cache coherency in a multi-processor system

Local memory with indicator bits to support concurrent DMA and CPU access

Fast hardware looping mechanism for cache cleaning and flushing of cache entries corresponding to a qualifier field

Embedded garbage collection

Accessing device driver memory in programming language representation

Mixed stack-based RISC processor

Test and skip processor instruction having at least one register operand

Memory management of local variables upon a change of context

Smart cache

Pre-decoding bytecode prefixes selectively incrementing stack machine program counter

CHAUVEL GERARD

Dirty cache line write back policy based on stack size trend information

Micro-sequence based security model

Multi-processor computing system having a JAVA stack machine and a RISC-based processor