Inventor
MALIK RAJEEV
US25 patents
⚠️ This page may combine multiple inventors who share the name “MALIK RAJEEV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
18 patentsUS7030012B2Apr 18, 2006
Method for manufacturing tungsten/polysilicon word line structure in vertical DRAM
IBM49 citations92
US6541810B2Apr 1, 2003
Modified vertical MOSFET and methods of formation thereof
IBM23 citations89
US7627836B2Dec 1, 2009
OPC trimming for performance
IBM15 citations84
US6809368B2Oct 26, 2004
TTO nitride liner for improved collar protection and TTO reliability
IBM15 citations84
US6620676B2Sep 16, 2003
Structure and methods for process integration in vertical DRAM cell fabrication
IBM14 citations84
US6509226B1Jan 21, 2003
Process for protecting array top oxide
IBM15 citations84
US7018779B2Mar 28, 2006
Apparatus and method to improve resist line roughness in semiconductor wafer processing
IBM13 citations82
US7446062B2Nov 4, 2008
Device having dual etch stop liner and reformed silicide layer and related methods
IBM5 citations74
US7306983B2Dec 11, 2007
Method for forming dual etch stop liner and protective layer in a semiconductor device
IBM9 citations74
US6908806B2Jun 21, 2005
Gate metal recess for oxidation protection and parasitic capacitance reduction
IBM10 citations74
US6790739B2Sep 14, 2004
Structure and methods for process integration in vertical DRAM cell fabrication
IBM11 citations74
US7776695B2Aug 17, 2010
Semiconductor device structure having low and high performance devices of same conductive type on same substrate
IBM2 citations63
US7683434B2Mar 23, 2010
Preventing cavitation in high aspect ratio dielectric regions of semiconductor device
IBM2 citations63
US7928571B2Apr 19, 2011
Device having dual etch stop liner and reformed silicide layer and related methods
IBM1 citations52
US7732270B2Jun 8, 2010
Device having enhanced stress state and related methods
IBM0 citations52
US7459384B2Dec 2, 2008
Preventing cavitation in high aspect ratio dielectric regions of semiconductor device
IBM0 citations52
US7446395B2Nov 4, 2008
Device having dual etch stop liner and protective layer
IBM0 citations52
US7348635B2Mar 25, 2008
Device having enhanced stress state and related methods
IBM0 citations52
INFINEON TECHNOLOGIES AG
5 patentsUS6635526B1Oct 21, 2003
Structure and method for dual work function logic devices in vertical DRAM process
INFINEON TECHNOLOGIES AG57 citations96
US6358867B1Mar 19, 2002
Orientation independent oxidation of silicon
INFINEON TECHNOLOGIES AG45 citations88
US6724054B1Apr 20, 2004
Self-aligned contact formation using double SiN spacers
INFINEON TECHNOLOGIES AG16 citations84
US6794242B1Sep 21, 2004
Extendible process for improved top oxide layer for DRAM array and the gate interconnects while providing self-aligned gate contacts
INFINEON TECHNOLOGIES AG12 citations74
US6794282B2Sep 21, 2004
Three layer aluminum deposition process for high aspect ratio CL contacts
INFINEON TECHNOLOGIES AG3 citations62