Inventor

DIVAKARUNI RAMA

US53 patents

⚠️ This page may combine multiple inventors who share the name “DIVAKARUNI RAMA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

DIVAKARUNI RAMA

IBM

High performance FET with elevated source/drain region

Double gate trench transistor

Shared body and diffusion contact structure and method for fabricating same

High density chip carrier with integrated passive devices

High density chip carrier with integrated passive devices

Transistors having independently adjustable parameters

Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation

Conductive contacts in semiconductor on insulator substrate

Method of fabricating semiconductor side wall fin

Nitrided STI liner oxide for reduced corner device impact on vertical device performance

Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base

Integration scheme for enhancing capacitance of trench capacitors

Trench isolation processes using polysilicon-assisted fill

Trench capacitor with an intrinsically balanced field across the dielectric

Notched collar isolation for suppression of vertical parasitic MOSFET and the method of preparing the same

Structure and process for fabricating a 6F2 DRAM cell having vertical MOSFET and large trench capacitance

Structure and process for 6F2 DT cell having vertical MOSFET and large storage capacitance

Pitcher-shaped active area for field effect transistor and method of forming same

Semiconductor fuses and antifuses in vertical DRAMS

Method of forming a trench capacitor DRAM cell

Capacitor trench-top dielectric for self-aligned device isolation

Bipolar transistor having reduced collector-base capacitance

Filling high aspect ratio isolation structures with polysilazane based material

Process flow for thick isolation collar with reduced length

Method of fabricating self-aligned bipolar transistor having tapered collector

Structure and method of self-aligned bipolar transistor having tapered collector

Structure of vertical strained silicon devices

High on-current device for high performance embedded DRAM (eDRAM) and method of forming the same

TTO nitride liner for improved collar protection and TTO reliability

Structure and methods for process integration in vertical DRAM cell fabrication

Pedestal collar structure for higher charge retention time in trench-type DRAM cells

Method of fabricating a bipolar transistor having reduced collector-base capacitance

High performance FET with elevated source/drain region

Method of fabricating semiconductor side wall fin

Method of fabricating semiconductor side wall fin

N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same

Structure and methods for process integration in vertical DRAM cell fabrication

N-channel metal oxide semiconductor (NMOS) driver circuit and method of making same

Pitcher-shaped active area for field effect transistor and method of forming same

PMOSFET device with localized nitrogen sidewall implantation

Method and device for array threshold voltage control by trapped charge in trench isolation

Method for dual sidewall oxidation in high density, high performance DRAMS

Forming collar structures in deep trench capacitors with thermally stable filler material

Method of simultaneously forming a line interconnect and a borderless contact to diffusion

Reduced cap layer erosion for borderless contacts

INFINEON TECHNOLOGIES CORP

Field-shield-trench isolation for gigabit DRAMs

Method for forming TTO nitride liner for improved collar protection and TTO reliability

INFINEON TECHNOLOGIES AG

Structure and method for dual work function logic devices in vertical DRAM process

EPLIS TECH INC

Conductive contacts in semiconductor on insulator substrate

ELPIS TECH INC

Conductive contacts in semiconductor on insulator substrate