Inventor

KRECH JR ALAN S

US45 patents

⚠️ This page may combine multiple inventors who share the name “KRECH JR ALAN S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KRECH JR ALAN S

HEWLETT PACKARD CO

Polyline and triangle strip data management techniques for enhancing performance of computer graphics system

Asynchronous FIFO queuing system operating with minimal queue status

Graphics accelerator with constant color identifier

Caching and coherency control of multiple geometry accelerators in a computer graphics system

Graphics accelerator with improved lighting processor

Graphics accelerator having minimal logic multiplexer system for sharing a microprocessor

System and method for dynamically allocating data among geometry accelerators in a computer graphics system

Caching and coherency control of multiple geometry accelerators in a computer graphics system

Computer graphics system utilizing parallel processing for enhanced performance

Enhanced test method for an application-specific memory scheme

Memory mapping techniques for enhancing performance of computer graphics system

Computer graphics system having double buffered vertex ram with granularity

Enhanced test system for an application-specific memory scheme

System and method for conditionally calculating exponential values in a geometry accelerator

Method and apparatus for clipping non-planar polygons

ROM-based control unit in a geometry accelerator for a computer graphics system

System and method for speculative execution in a geometry accelerator

Graphic accelerator architecture using two graphics processing units for processing aspects of pre-rasterized graphics primitives and a control circuitry for relaying pass-through information

Distributed branch logic system and method for a geometry accelerator

Methods and apparatus for electrically verifying a functional unit contained within an integrated cirucuit

ROM-based control units in a geometry accelerator for a computer graphics system

Centralized branch intelligence system and method for a geometry accelerator

AGILENT TECHNOLOGIES INC

Memory tester tests multiple DUT&#39;s per test site

Method and apparatus for coordinating program execution in a site controller with pattern execution in a tester

Method and apparatus for executing a program using primary, secondary and tertiary memories

Method and apparatus for inserting programmable latency between address and data information in a memory tester

Algorithmically programmable memory tester with history FIFO&#39;s that aid in error analysis and recovery

Algorithmically programmable memory tester with breakpoint trigger, error jamming and &#39;scope mode that memorizes target sequences

Algorithmically programmable memory tester with test sites operating in a slave mode

Method and apparatus for administration of extended memory

Memory tester omits programming of addresses in detected bad columns

Apparatus and method for storing information during a test program

Memory tester uses arbitrary dynamic mappings to serialize vectors into transmitted sub-vectors and de-serialize received sub-vectors into vectors

Method and apparatus for administering inversion property in a memory tester

Method and apparatus for no-latency conditional branching

Recapture of a portion of a displayed waveform without loss of existing data in the waveform display

Simultaneous display of data gathered using multiple data gathering mechanisms

ADVANTEST CORP

Staged buffer caching in a system for testing a device under test

Flexible test site synchronization

Testing memory devices with parallel processing operations

Method and system for advanced fail data transfer mechanisms

HEWLETT PACKARD COMPNAY

Method and apparatus for processing graphics primitives in multiple modes using reconfigurable hardware

VERIGY PTE LTD

Reconstruction of non-deterministic algorithmic tester stimulus used as input to a device under test

HEWLETT PACKARD COMPANU

Method and apparatus for processing primitives in a computer graphics display system

VERIGY PTE LTD SINGAPORE

Memory device fail summary data reduction for improved redundancy analysis

Memory tester tests multiple DUT's per test site

Algorithmically programmable memory tester with history FIFO's that aid in error analysis and recovery

Algorithmically programmable memory tester with breakpoint trigger, error jamming and 'scope mode that memorizes target sequences