Inventor

SIO KAM-TOU

TW119 patents

⚠️ This page may combine multiple inventors who share the name “SIO KAM-TOU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SIO KAM-TOU

TAIWAN SEMICONDUCTOR MFG CO LTD

Semiconductor device integrating backside power grid and related integrated circuit and fabrication method

Integrated circuit with mixed row heights

Semiconductor devices with backside power distribution network and frontside through silicon via

Method of forming semiconductor device including source/drain contact having height below gate stack

Fin field-effect transistor and method of forming the same

Metal rail conductors for non-planar semiconductor devices

Metal rail conductors for non-planar semiconductor devices

Pin access hybrid cell height design

System and method for calculating cell edge leakage

Method of manufacturing conductors and semiconductor device which includes conductors

System for and method of manufacturing a layout design of an integrated circuit

Semiconductor device including source/drain contact having height below gate stack

Power strap structure for high performance and low current density

Middle end-of-line strap for standard cell

Dual power structure with connection pins

High fin cut fabrication process

Semiconductor device including source/drain contact having height below gate stack

Manufacturing method for semiconductor device

Semiconductor device including source/drain contact having height below gate stack

Integrated circuit structure with hybrid cell design

Middle-end-of-line strap for standard cell

Decoupling capacitors with back side power rails

Semiconductor devices with backside power distribution network and frontside through silicon via

Integrated circuit with mixed row heights

Semiconductor device including a layer between a source/drain region and a substrate

Integrated circuit including super via and method of making

Method and system of manufacturing conductors and semiconductor device which includes conductors

Circuit layout

Semiconductor device including source/drain contact having height below gate stack

Middle-end-of-line strap for standard cell

Integrated circuit including supervia and method of making

Pin access hybrid cell height design

Via rail solution for high power electromigration

Method and system of manufacturing conductors and semiconductor device which includes conductors

System for and method of manufacturing an integrated circuit

High-density semiconductor device

FinFET switch

Middle-end-of-line strap for standard cell

System and method for calculating cell edge leakage

Power strap structure for high performance and low current density

Semiconductor device including source/drain contact having height below gate stack

Semiconductor device which includes Fins

FinFET switch

Via rail solution for high power electromigration

Dual power structure with connection pins

Middle end-of-line strap for standard cell

Power strap structure for high performance and low current density

Layout modification method and system

Interconnect metal layout for integrated circuit

TZENG JIANN-TYNG

Integrated circuit layout having mixed track standard cell