Inventor

SHUMARAYEV SERGEY

US163 patents

⚠️ This page may combine multiple inventors who share the name “SHUMARAYEV SERGEY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHUMARAYEV SERGEY

ALTERA CORP

Signal loss detector for high-speed serial interface of a programmable logic device

Driver circuitry for programmable logic devices

Interconnection and input/output resources for programmable logic integrated circuit devices

Programmable logic device configured to accommodate multiplication

Dynamically-adjustable differential output drivers

Dynamically adjustable termination impedance control techniques

Adjustable differential input and output drivers

Programmable termination with DC voltage level control

High-performance interconnect

Apparatus and methods for adjusting performance characteristics and power consumption of programmable logic devices

Transmitter with multiple phase locked loops

Clock distribution techniques for channels

Techniques for dynamically adjusting the frequency range of phase-locked loops

Adaptive equalization methods and apparatus

Low-power transceiver architectures for programmable logic integrated circuit devices

Programmable termination with DC voltage level control

Programmable termination with DC voltage level control

Adjustable differential input and output drivers

Systems and methods for simulating link performance

Techniques for compensating delays in clock signals on integrated circuits

Flexible high-speed serial interface architectures for programmable integrated circuit devices

Comparator offset cancellation assisted by PLD resources

Techniques for reconfiguring programmable circuit blocks

H-tree driver circuitry

Interconnection and input/output resources for programmable logic integrated circuit devices

Dynamically-adjustable differential output drivers

Interconnection and input/output resources for programmable logic integrated circuit devices

Integrated circuit serializers with two-phase global master clocks

Clock data recovery circuitry and phase locked loop circuitry with dynamically adjustable bandwidths

Interconnection and input/output resources for programmable logic integrated circuit devices

Interconnection resources for programmable logic integrated circuit devices

Interconnection and input/output resources for programable logic integrated circuit devices

Embedded memory blocks for programmable logic

Embedded memory blocks for programmable logic

High-performance interconnect

Phase-locked loop architecture and clock distribution system

Transceiver circuitry with multiple phase-locked loops

Apparatus and methods of receiver offset calibration

DING WEIQI

On-chip eye viewer architecture for highspeed transceivers

On-chip full eye viewer architecture

Analog signal test circuits and methods

Techniques for reducing duty cycle distortion in periodic signals

LI PENG

Integrated optical-electronic interface in programmable integrated circuit device

Simulation tool for high-speed communications links

SU XIAOYAN

Reconfigurable equalization architecture for high-speed receivers

Receiver equalizer circuitry with offset voltage compensation for use on integrated circuits

PHAM TIEN DUC

Phase-locked loop architecture and clock distribution system

PAN MINGDE

Multi-level amplitude signaling receiver

WONG WILSON

Decoupling capacitor control circuitry

CHAN ALLEN

PLD architecture optimized for 10G Ethernet physical layer solution