Inventor

PANWAR RAMESH

US68 patents

⚠️ This page may combine multiple inventors who share the name “PANWAR RAMESH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PANWAR RAMESH

SUN MICROSYSTEMS INC

Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency

Apparatus for dynamically reconfiguring a processor

System for allocation of execution resources amongst multiple executing processes

Method for dynamically reconfiguring a processor

Method and apparatus for moderating current demand in an integrated circuit processor

Apparatus for executing coded dependent instructions having variable latencies

Method for thermal overload detection and prevention for an intergrated circuit processor

Cache memory array which stores two-way set associative data

Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine

Method for precise architectural update in an out-of-order processor

Computer product for precise architectural update in an out-of-order processor

Method for inhibiting thrashing in a multi-level non-blocking cache system

Multi-level non-blocking cache system with inhibiting thrashing

Pipeline processor and computing system including an apparatus for tracking pipeline resources

Reducing data dependent conflicts by converting single precision instructions into microinstructions using renamed phantom registers in a processor having double precision registers

In-line bank conflict detection and resolution in a multi-ported non-blocking cache

Method for non-intrusive cache fills and handling of load misses

Apparatus for delivering precise traps and interrupts in an out-of-order processor

Apparatus for restraining over-eager load boosting in an out-of-order machine using a memory disambiguation buffer for determining dependencies

Method for restraining over-eager load boosting using a dependency color indicator stored in cache with both the load and store instructions

System for thermal overload detection and prevention for an integrated circuit processor

Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache

Method for tracking pipeline resources in a superscalar processor

Apparatus for handling register windows in an out-of-order processor

Apparatus for enforcing true dependencies in an out-of-order processor

Method for speculative calculation of physical register addresses in an out of order processor

Method for enforcing true dependencies in an out-of-order processor

Apparatus for generating out-of-order results and out-of-order condition codes in a processor

JUNIPER NETWORKS INC

Sharing a second tier cache memory in a multi-processor

Methods and apparatus related to packet classification associated with a multi-stage switch

Content service aggregation system

Methods and apparatus related to packet classification based on range values

Content service aggregation system

Content service aggregation device for a data center

Managing ownership of a full cache line using a store-create operation

Processing packets in cache memory

Ring-based memory requests in a shared memory multi-processor

Ring based multi-processing system

Enforcement of cache coherency policies using process synchronization services

Content service aggregation system

Methods and apparatus for packet classification based on policy vectors

Application processing employing a coprocessor

Methods and apparatus for packet classification based on multiple conditions

Methods and apparatus for range matching during packet classification based on a linked-node structure

PANWAR RAMESH

Methods and apparatus for producing a hash value based on a hash function

Providing privacy within computer networks using anonymous cookies

Methods and apparatus for packet classification based on multiple conditions

GOEL DEEPAK

Methods and apparatus to implement except condition during data packet classification

Methods and apparatus for compression in packet classification

Methods and apparatus for range matching during packet classification based on a linked-node structure