Inventor

JOSHI RAJIV V

US219 patents

⚠️ This page may combine multiple inventors who share the name “JOSHI RAJIV V”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

JOSHI RAJIV V

IBM

FET channel having a strained lattice structure along multiple surfaces

High performance FET with elevated source/drain region

T-Ram array having a planar cell structure and method for fabricating the same

Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD

Non-volatile magnetic memory cell and devices

Refractory metal capped low resistivity metal conductor lines and vias

Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps

Refractory metal capped low resistivity metal conductor lines and vias

Silicon/carbon protection of metallic magnetic structures

Dynamic control of back gate bias in a FinFET SRAM cell

Method and computer program for efficient cell failure rate estimation in cell arrays

Row circuit ring oscillator method for evaluating memory cell performance

Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability

CMOS well structure and method of forming the same

Low-power band-gap reference and temperature sensor circuit

Method and system for improving the performance on SOI memory arrays in an SRAM architecture system

Low-power band-gap reference and temperature sensor circuit

Method for selective deposition of refractory metals on silicon substrates and device formed thereby

Temperature sensor for high power very large scale integration circuits

Silicon on insulator field effect transistors having shared body contact

Refractory metal capped low resistivity metal conductor lines and vias

Refractory metal capped low resistivity metal conductor lines and vias formed using PVD and CVD

Storage array such as a SRAM with reduced power requirements

Low-power DC voltage generator system

T-RAM structure having dual vertical devices and method for fabricating the same

Low-power DC voltage generator system

Refractory metal capped low resistivity metal conductor lines and vias

Refractory metal capped low resistivity metal conductor lines and vias

Refractory metal capped low resistivity metal conductor lines and vias

Semiconductor device and wafer structure having a planar buried interconnect by wafer bonding

High speed silicon-based lateral junction photodetectors having recessed electrodes and thick oxide to reduce fringing fields

Interconnect structure and method for forming the same

Simultaneous grain modulation for BEOL applications

Energy efficient storage device using per-element selectable power supply voltages

Dynamic leakage control circuit

Method for making a FET channel

SRAM with dynamically asymmetric cell

T-RAM cell having a buried vertical thyristor and a pseudo-TFT transfer gate and method for fabricating the same

Memory array with dual wordline operation

SRAM with improved noise sensitivity

Temperature programmable timing delay system

Semiconductor device utilizing alignment marks for globally aligning the front and back sides of a semiconductor substrate

Flash memory structure having double celled elements and method for fabricating the same

Hierarchical bitline DRAM architecture system

Folded-bitline dual-port DRAM architecture system

Method for depositing tungsten on silicon in a non-self-limiting CVD process and semiconductor device manufactured thereby

Low stress tungsten films by silicon reduction of WF6

Graded oxide/nitride via structure and method of fabrication therefor

JOSHI RAJIV V

Methodology for correlated memory fail estimations

In-situ design method and system for improved memory yield