Inventor

HERRERO ENRIC

ES4 patents

⚠️ This page may combine multiple inventors who share the name “HERRERO ENRIC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAMIREZ TANAUSU

2 patents

US9112537B2Aug 18, 2015

Content-aware caches for reliability

RAMIREZ TANAUSU8 citations79

US9286172B2Mar 15, 2016

Fault-aware mapping for shared last level cache (LLC)

RAMIREZ TANAUSU3 citations68

VERA XAVIER

2 patents

US9405647B2Aug 2, 2016

Register error protection through binary translation

VERA XAVIER2 citations60

US9170947B2Oct 27, 2015

Recovering from data errors using implicit redundancy

VERA XAVIER3 citations60