Inventor
ERWIN BRIAN M
US25 patents
⚠️ This page may combine multiple inventors who share the name “ERWIN BRIAN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
21 patentsUS9401336B2Jul 26, 2016
Dual layer stack for contact formation
IBM48 citations93
US9601423B1Mar 21, 2017
Under die surface mounted electrical elements
IBM4 citations73
US9565777B1Feb 7, 2017
Security mesh and method of making
IBM4 citations73
US9324669B2Apr 26, 2016
Use of electrolytic plating to control solder wetting
IBM5 citations73
US10756041B1Aug 25, 2020
Finned contact
IBM3 citations71
US9190376B1Nov 17, 2015
Organic coating to inhibit solder wetting on pillar sidewalls
IBM2 citations63
US11009545B2May 18, 2021
Integrated circuit tester probe contact liner
IBM0 citations62
US10892249B2Jan 12, 2021
Carrier and integrated memory
IBM0 citations62
US10566275B2Feb 18, 2020
Element place on laminates
IBM1 citations62
US10224269B2Mar 5, 2019
Element place on laminates
IBM1 citations62
US9961765B2May 1, 2018
Security mesh and method of making
IBM0 citations52
US9640492B1May 2, 2017
Laminate warpage control
IBM1 citations52
US10840214B2Nov 17, 2020
Carrier and integrated memory
IBM0 citations51
US10670653B2Jun 2, 2020
Integrated circuit tester probe contact liner
IBM0 citations51
US10515929B2Dec 24, 2019
Carrier and integrated memory
IBM0 citations51
US10431563B1Oct 1, 2019
Carrier and integrated memory
IBM0 citations51
US9728440B2Aug 8, 2017
Non-transparent microelectronic grade glass as a substrate, temporary carrier or wafer
IBM0 citations51
US9214385B2Dec 15, 2015
Semiconductor device including passivation layer encapsulant
IBM0 citations51
US9431359B2Aug 30, 2016
Coaxial solder bump support structure
IBM0 citations50
US9754823B2Sep 5, 2017
Substrate including selectively formed barrier layer
IBM0 citations47
US9748135B2Aug 29, 2017
Substrate including selectively formed barrier layer
IBM0 citations47