Inventor

KENNEL HAROLD

US30 patents

⚠️ This page may combine multiple inventors who share the name “KENNEL HAROLD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KENNEL HAROLD

INTEL CORP

Nitrogen controlled growth of dislocation loop in stress enhanced transistor

Pulsed laser anneal process for transistors with partial melt of a raised source-drain

Nitrogen controlled growth of dislocation loop in stress enhanced transistor

Temperature measurement with reduced extraneous infrared in a processing chamber

Nitrogen controlled growth of dislocation loop in stress enhanced transistor

Ferroelectric gate stack for band-to-band tunneling reduction

Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)

Pulsed laser anneal process for transistor with partial melt of a raised source-drain

Channel layer formed in an art trench

Ferroelectric gate stack for band-to-band tunneling reduction

Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly

Integrated circuit structures having germanium-based channels

Integrated circuit structures having germanium-based channels

Amorphization and regrowth of source-drain regions from the bottom-side of a semiconductor assembly

Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)

Contact stacks to reduce hydrogen in semiconductor devices

Contacts to n-type transistors with X-valley layer over L-valley channels

Stacked thin film transistors

Integrated circuit structures having germanium-based channels

Source/drain recess etch stop layers and bottom wide-gap cap for III-V MOSFETs

Sub-second annealing processes for semiconductor devices

Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts

High performance semiconductor oxide material channel regions for NMOS

Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)

Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)

Systems, methods and devices for isolation for subfin leakage

Double-sided integrated circuit transistor structures with depopulated bottom channel regions

Source or drain structures for germanium N-channel devices

JENSEN JACOB

Pulsed laser anneal process for transistors with partial melt of a raised source-drain

Selective laser annealing process for buried regions in a MOS device