Inventor
NG CHIT HWEI
SG23 patents
⚠️ This page may combine multiple inventors who share the name “NG CHIT HWEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
CHARTERED SEMICONDUCTOR MFG
20 patentsUS6410376B1Jun 25, 2002
Method to fabricate dual-metal CMOS transistors for sub-0.1 μm ULSI integration
CHARTERED SEMICONDUCTOR MFG165 citations98
US6670237B1Dec 30, 2003
Method for an advanced MIM capacitor
CHARTERED SEMICONDUCTOR MFG82 citations97
US6709918B1Mar 23, 2004
Method for making a metal-insulator-metal (MIM) capacitor and metal resistor for a copper back-end-of-line (BEOL) technology
CHARTERED SEMICONDUCTOR MFG87 citations96
US6730573B1May 4, 2004
MIM and metal resistor formation at CU beol using only one extra mask
CHARTERED SEMICONDUCTOR MFG96 citations95
US6716693B1Apr 6, 2004
Method of forming a surface coating layer within an opening within a body by atomic layer deposition
CHARTERED SEMICONDUCTOR MFG49 citations93
US7067869B2Jun 27, 2006
Adjustable 3D capacitor
CHARTERED SEMICONDUCTOR MFG23 citations92
US6902981B2Jun 7, 2005
Structure and process for a capacitor and other devices
CHARTERED SEMICONDUCTOR MFG22 citations92
US6903013B2Jun 7, 2005
Method to fill a trench and tunnel by using ALD seed layer and electroless plating
CHARTERED SEMICONDUCTOR MFG44 citations92
US6638844B1Oct 28, 2003
Method of reducing substrate coupling/noise for radio frequency CMOS (RFCMOS) components in semiconductor technology by backside trench and fill
CHARTERED SEMICONDUCTOR MFG29 citations92
US6624040B1Sep 23, 2003
Self-integrated vertical MIM capacitor in the dual damascene process
CHARTERED SEMICONDUCTOR MFG46 citations92
US6375857B1Apr 23, 2002
Method to form fuse using polymeric films
CHARTERED SEMICONDUCTOR MFG12 citations74
US6852605B2Feb 8, 2005
Method of forming an inductor with continuous metal deposition
CHARTERED SEMICONDUCTOR MFG10 citations73
US6689643B2Feb 10, 2004
Adjustable 3D capacitor
CHARTERED SEMICONDUCTOR MFG7 citations73
US6548367B1Apr 15, 2003
Method to fabricate MIM capacitor with a curvillnear surface using damascene process
CHARTERED SEMICONDUCTOR MFG7 citations73
US7250669B2Jul 31, 2007
Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
CHARTERED SEMICONDUCTOR MFG6 citations72
US6869884B2Mar 22, 2005
Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
CHARTERED SEMICONDUCTOR MFG7 citations72
US6608362B1Aug 19, 2003
Method and device for reducing capacitive and magnetic effects from a substrate by using a schottky diode under passive components
CHARTERED SEMICONDUCTOR MFG8 citations72
US6821904B2Nov 23, 2004
Method of blocking nitrogen from thick gate oxide during dual gate CMP
CHARTERED SEMICONDUCTOR MFG3 citations62
US7060193B2Jun 13, 2006
Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits
CHARTERED SEMICONDUCTOR MFG3 citations60
US7323736B2Jan 29, 2008
Method to form both high and low-k materials over the same dielectric region, and their application in mixed mode circuits
CHARTERED SEMICONDUCTOR MFG4 citations59