Inventor

TAKACH ANDRES R

US6 patents

⚠️ This page may combine multiple inventors who share the name “TAKACH ANDRES R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GUTBERLET PETER PIUS

2 patents

US7412684B2Aug 12, 2008

Loop manipulation in a behavioral synthesis tool

GUTBERLET PETER PIUS12 citations82

US7353491B2Apr 1, 2008

Optimization of memory accesses in a circuit design

GUTBERLET PETER PIUS6 citations69

MENTOR GRAPHICS CORP

2 patents

US7840931B2Nov 23, 2010

Loop manipulation if a behavioral synthesis tool

MENTOR GRAPHICS CORP8 citations80

US10515168B1Dec 24, 2019

Formal verification using microtransactions

MENTOR GRAPHICS CORP6 citations79

CALYPTO DESIGN SYSTEMS INC

1 patent

US9817929B1Nov 14, 2017

Formal verification using microtransactions

CALYPTO DESIGN SYSTEMS INC10 citations79

CONDON ROBERT J

1 patent

US8219949B2Jul 10, 2012

Nonsequential hardware design synthesis verification

CONDON ROBERT J2 citations47