Inventor

AU MARIO

US20 patents

⚠️ This page may combine multiple inventors who share the name “AU MARIO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

AU MARIO

INTEGRATED DEVICE TECH

Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays

Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein

Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation

Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration

Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes

FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same

FIFO memory devices and methods of operating FIFO memory devices having multi-port cache memory devices therein

Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation

Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system

Multi-function queue to support data offload, protocol translation and pass-through FIFO

Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system

Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory system

FIFO memory devices having multi-port cache and extended capacity memory devices therein with retransmit capability

Multi-queue FIFO memory devices that support a backed-off standard mode of operation and methods of operating same

Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system

Partial packet write and write data filtering in a multi-queue first-in first-out memory system

Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system

Serial buffer supporting virtual queue to physical memory mapping

Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory system

AU MARIO

Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system