Inventor

RAHMAN ARDASHEIR

US22 patents

⚠️ This page may combine multiple inventors who share the name “RAHMAN ARDASHEIR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RAHMAN ARDASHEIR

IBM

Three-dimensional monolithic vertical field effect transistor logic gates

Staggered stacked vertical crystalline semiconducting channels

Nanosheet device with tall suspension and tight contacted gate poly-pitch

Three-dimensional stacked vertical transport field effect transistor logic gate with buried power bus

Gate all-around device with through-stack nanosheet 2D channel

Looped long channel field-effect transistor

Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers

Static random access memory using vertical transport field effect transistors

Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers

Source and drain contact cut last process to enable wrap-around-contact

Staggered stacked vertical crystalline semiconducting channels

Static random access memory using vertical transport field effect transistors

Selective source/drain recess for improved performance, isolation, and scaling

Nanosheet structures having vertically oriented and horizontally stacked nanosheets

Source and drain contact cut last process to enable wrap-around-contact

Spacer-confined epitaxial growth

Conformal dielectric cap for subtractive vias

Forming crossbar and non-crossbar transistors on the same substrate

Vertical field-effect transistor with T-shaped gate

Self aligned block masks for implantation control

Integrated input output and logic device for nanosheet technology

ELPIS TECH INC

Three-dimensional monolithic vertical field effect transistor logic gates