Inventor

HELM MARK

US44 patents

⚠️ This page may combine multiple inventors who share the name “HELM MARK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HELM MARK

MICRON TECHNOLOGY INC

Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate

Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry

Method of forming CMOS integrated circuitry having halo regions

CMOS integrated circuitry with Halo and LDD regions

Integrated circuitry comprising halo regions and LDD regions

Method of forming CMOS integrated circuitry

Semiconductor processing method of forming complementary n-type doped and p-type doped active regions within a semiconductor substrate

Method of forming CMOS integrated circuitry

Method for forming standard voltage threshold and low voltage threshold MOSFET devices

Non-volatile memory cell healing

Method of forming CMOS integrated circuitry

Method of forming CMOS integrated circuitry

Method of forming CMOS integrated circuitry

Memory array reset read operation

Formation of standard voltage threshold and low voltage threshold MOSFET devices

Formation of standard voltage threshold and low voltage threshold MOSFET devices

Structure and method of fabricating a transistor having a trench gate

Apparatus, systems, and methods to operate a memory

Formation of standard voltage threshold and low voltage threshold MOSFET devices

Select gate transistors and methods of operating the same

Formation of standard voltage threshold and low voltage threshold MOSFET devices

Structure and method of fabricating a transistor having a trench gate

Formation of standard voltage threshold and low voltage threshold MOSFET devices

Structure and method of fabricating a transistor having a trench gate

Memory array reset read operation

Memory array reset read operation

Apparatus, systems, and methods to operate a memory

Memory program disturb reduction

Formation of standard voltage threshold and low voltage threshold MOSFET devices

INTEL CORP

Flash memory device with improved erase operation

Three dimensional storage cell array with highly dense and scalable word line design approach

Method and apparatus for shielded read to reduce parasitic capacitive coupling

Three dimensional memory control circuitry

Three dimensional storage cell array with highly dense and scalable word line design approach

ROUND ROCK RES LLC

Formation of standard voltage threshold and low voltage threshold MOSFET devices

Formation of standard voltage threshold and low voltage threshold MOSFET devices

Structure and method of fabricating a transistor having a trench gate

MIHNEA ANDREI

Non-volatile memory cell healing

Non-volatile memory cell healing

GOLDMAN MATTHEW

Method and system to obtain state confidence data using multistrobe read of a non-volatile memory

HELM MARK

Three dimensional memory control circuitry

GODA AKIRA

Memory program disturb reduction

CHANDRASEKHAR UDAY

Memory kink checking

SMITH MICHAEL

Structure and method of fabricating a transistor having a trench gate