Inventor

SIEGEL MICHAEL S

US70 patents

⚠️ This page may combine multiple inventors who share the name “SIEGEL MICHAEL S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SIEGEL MICHAEL S

IBM

System and method for automatic management of many computer data processing system pipes

Method and system in a local area network switch for dynamically changing operating modes

Memory system with apparatus and method to enable balanced bandwidth utilization

Execution unit with an integrated vector operation capability

Apparatus and method for determining operational mode for a station entering a network

Method and system of automatically configuring a LAN switch portof a multi-port LAN switch based on an attached device type

Integrated circuit and data processing system having a configurable cache directory for an accelerator

Pre-transmission data reordering for a serial interface

Coherent attached processor proxy having hybrid directory

Translation invalidation in a translation cache serving an accelerator

Techniques for issuing interrupts in a data processing system with multiple scopes

Managing efficient selection of a particular processor thread for handling an interrupt

Coherency error detection and reporting in a processor

Data recovery for coherent attached processor proxy

Master requesting missing segments of a cache line for which the master has coherence ownership

Coherency overcommit

Coherency overcommit

Managing efficient selection of a particular processor thread for handling an interrupt

Integrated circuit and data processing system supporting address aliasing in an accelerator

Techniques for managing a hang condition in a data processing system with shared memory

Determining command rate based on dropped commands

Determining command rate based on dropped commands

Coherent proxy for attached processor

Balanced bandwidth utilization

Integrated circuit design structure for an asychronous data interface

Method and system for nonsequential execution of intermixed scalar and vector instructions in a data processing system utilizing a finish instruction array

Broadcast scope selection in a data processing system utilizing a memory topology data structure

Speculative delivery of data from a lower level of a memory hierarchy in a data processing system

Split transaction coherency protocol in a data processing system

Reducing translation latency within a memory management unit using external caching structures

Reducing translation latency within a memory management unit using external caching structures

Decreasing the data handoff interval in a multiprocessor data processing system based on an early indication of a systemwide coherence response

Selection of post-request action based on combined response and input from the request source

Command rate configuration in data processing system

Selection of post-request action based on combined response and input from the request source

Programmable coherent proxy for attached processor

Coherent attached processor proxy supporting coherence state update in presence of dispatched master

Programmable coherent proxy for attached processor

Coherent attached processor proxy supporting coherence state update in presence of dispatched master

Command rate configuration in data processing system

Epoch-based recovery for coherent attached processor proxy

Coherent attached processor proxy having hybrid directory

Epoch-based recovery for coherent attached processor proxy

Integrated circuit and data processing system supporting attachment of a real address-agnostic accelerator

GUTHRIE GUY L

Lateral cache-to-cache cast-in

Lateral castout (LCO) of victim cache line in data-invalid state

Handling castout cache lines in a victim cache

CARPENTER BRIAN E

Method for managing of denial of service attacks using bandwidth allocation technology

LEMKE SCOTT J

Asynchronous data interface

GANFIELD PAUL A

Memory coherence directory supporting remotely sourced requests of nodal scope