Inventor

POPLACK MITCHELL G

US51 patents

⚠️ This page may combine multiple inventors who share the name “POPLACK MITCHELL G”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

POPLACK MITCHELL G

CADENCE DESIGN SYSTEMS INC

System and method of encoding in a serializer/deserializer

Data routing and multiplexing architecture to support serial links and advanced relocation of emulation models

Compacting trace data generated by emulation processors during emulation of a circuit design

Method and system for modeling a flip-flop of a user design

Hardware emulation method and system using a port time shift register

System and method of encoding in a serializer/deserializer

Method and apparatus for sharing data between discrete clusters of processors

Hardware emulator having a variable input emulation group

Relocate targets to different domains in an emulator

Inline hardware compression subsystem for emulation trace data

Method and apparatus for designing an emulation chip using a selectable fastpath topology

Emulation system supporting representation of four-state signals

Dynamic one-bit multiplexing switch for emulation interconnect

Framing protocol supporting low-latency serial interface in an emulation system

Emulation system supporting four-state for sequential logic circuits

Method and system to mitigate large power load steps due to intermittent execution in a computation system

Enhanced control system for flexible programmable logic and synchronization

Multiphase I/O for processor-based emulation system

System and method for concurrent interconnection diagnostics field

System for concurrent target diagnostics field

Systems and methods for handling DPI messages outgoing from an emulator system

Systems and methods for intercycle gap refresh and backpressure management

Method and system to transfer data between components of an emulation system

Method and system for dynamic selection of a memory read port

Hardware emulator having a selectable write-back processor unit

Architecture and methodology for tuning clock phases to minimize latency in a serial interface

Emulation system supporting computation of four-state combinational functions

Systems and methods for emulation data array compaction

Dynamic netlist modification of compacted data arrays in an emulation system

Method and system to mitigate large power load steps due to intermittent execution in a computation system

Method and apparatus for increasing the efficiency of an emulation engine

Emulator synchronization subsystem with enhanced slave mode

Systems and methods for reducing latency when transferring I/O between an emulator and target device

Method and apparatus for synchronizing processors in a hardware emulation system

Embedded processor architecture with shared memory with design under test

System for concurrent target diagnostics field

Method and system for trace compaction during emulation of a circuit design

System interconnect architecture using dynamic bitwise switch and low-latency input/output

Tiled datamesh architecture

Systems and methods for enhanced compression of trace data in an emulation system

Method and system for providing additional look-up tables

QUICKTURN DESIGN SYSTEMS INC

System and method for providing flexible signal routing and timing

Extensible memory architecture and communication protocol for supporting multiple devices in low-bandwidth, asynchronous applications

Emulation processor interconnection architecture

System and method for configuring communication systems

Optimized interface for simulation and visualization data transfer between an emulation system and a simulator

System and method for identifying target systems

System and method for resolving artifacts in differential signals

BERSHTEYN MIKHAIL

Emulation system with improved reliability of interconnect and a method for programming such interconnect

Hardware emulation system having a heterogeneous cluster of processors