Inventor

OLDIGES PHILIP J

US50 patents

⚠️ This page may combine multiple inventors who share the name “OLDIGES PHILIP J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OLDIGES PHILIP J

IBM

Vertical FET with reduced parasitic capacitance

Structure and method of making double-gated self-aligned finFET having gates of different lengths

Thin channel FET with recessed source/drains and extensions

Stressed channel FET with source/drain buffers

MOSFET structure with ultra-low K spacer

Apparatus and method for hardening latches in SOI CMOS devices

Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levels

Method for soft error modeling with double current pulse

Hybrid SOI/bulk semiconductor transistors

Hybrid SOI/bulk semiconductor transistors

Hybrid SOI-bulk semiconductor transistors

Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors

Heater for annealing trapped charge in a semiconductor device

Vertical field effect transistor with improved reliability

Asymmetric finFET memory access transistor

Asymmetric finFET memory access transistor

Radiation tolerant device structure

Non-uniform gate dielectric for U-shape MOSFET

Vertical FET with reduced parasitic capacitance

Ultra-thin semiconductor on insulator metal gate complementary field effect transistor with metal gate and method of forming thereof

Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors

Techniques for quantifying fin-thickness variation in FINFET technology

Techniques for quantifying fin-thickness variation in FINFET technology

Stressed channel FET with source/drain buffers

Reducing error rates with alpha particle protection

Apparatus for modeling of FinFET width quantization

Methods for modeling of FinFET width quantization

Vertical field effect transistor with improved reliability

Vertical FET with reduced parasitic capacitance

Vertical FET with reduced parasitic capacitance

Non-uniform gate dielectric for U-shape MOSFET

Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers

Apparatus and method for hardening latches in SOI CMOS devices

Embedded stressor for semiconductor structures

Method and structure for improving uniformity of passive devices in metal gate technology

Capacitor below the buried oxide of SOI CMOS technologies for protection against soft errors

Method of making double-gated self-aligned finFET having gates of different lengths

Structure for planar SOI substrate with multiple orientations

Methods for modeling of FinFET width quantization

Method and structure for dielectric isolation in a fin field effect transistor

CHENG KANGGUO

Implant free extremely thin semiconductor devices

Implant free extremely thin semiconductor devices

GUO DECHAO

Stressor in planar field effect transistor device

Embedded stressor for semiconductor structures

GLOBALFOUNDRIES INC

FinFET PCM access transistor having gate-wrapped source and drain regions

FinFET PCM access transistor having gate-wrapped source and drain regions

CHEN TZE-CHIANG

Interface structure for channel mobility improvement in high-k metal gate stack

CHIDAMBARRAO DURESETI

Minimizing leakage current and junction capacitance in CMOS transistors by utilizing dielectric spacers

NING TAK H

Devices having reduced susceptibility to soft-error effects and method for fabrication

HAKEY MARK C

Structure for heavy ion tolerant device, method of manufacturing the same and structure thereof