Inventor

WARNOCK JAMES D

US52 patents

⚠️ This page may combine multiple inventors who share the name “WARNOCK JAMES D”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WARNOCK JAMES D

IBM

Dynamic and preset static multiplexer in front of latch circuit for use in static circuits

Method of forming uniformly thin, isolated silicon mesas on an insulating substrate

Apparatus and method for hardening latches in SOI CMOS devices

Scannable dynamic logic latch circuit

Parallel field effect transistor structure having a body contact

Methods and apparatus for operating master-slave latches

Power grid generation through modification of an initial power grid based on power grid analysis

Reduced pessimism clock gating tests for a timing analysis tool

Programmable delay circuit including hybrid fin field effect transistors (finFETs)

Debugging scan latch circuits using flip devices

Signal distribution in integrated circuit using optical through silicon via

Programmable local clock buffer

Methods for modeling latch transparency

Pessimism reduction in cross-talk noise determination used in integrated circuit design

Priority based circuit synthesis

Programmable clock division methodology with in-context frequency checking

Margin improvement for configurable local clock buffer

High-speed level sensitive scan design test scheme with pipelined test clocks

Debugging scan latch circuits using flip devices

Device-based random variability modeling in timing analysis

Pulsed local clock buffer (LCB) characterization ring oscillator

Operating pulsed latches on a variable power supply

Adjusting scan connections based on scan control locations

Programmable delay circuit including hybrid fin field effect transistors (finFETs)

Transmission gate multiplexer

Performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution network

Performance-screen ring oscillator (PSRO) using an integrated circuit test signal distribution network

Debugging scan latch circuits using flip devices

Voltage droop reduction in a processor

Signal distribution in integrated circuit using optical through silicon via

Apparatus and method for hardening latches in SOI CMOS devices

Initializing scannable and non-scannable latches from a common clock buffer

Initializing scannable and non-scannable latches from a common clock buffer

Low-power multi-output local clock buffer

Method and apparatus for a configurable low power high fan-in multiplexer

Methods for modeling latch transparency

Operating pulsed latches on a variable power supply

Transmission gate multiplexer

Programmable clock division methodology with in-context frequency checking

Priority based circuit synthesis

Programmable delay circuit including hybrid fin field effect transistors (finFETs)

Adjusting scan connections based on scan control locations

Optimal spare latch selection for metal-only ECOs

Programmable integrated circuit standard cell

Programmable integrated circuit standard cell

Validating variation of timing constraint measurements

Validating variation of timing constraint measurements

Clock skew analysis and optimization

GLOBALFOUNDRIES INC

On-chip sensor for monitoring active circuits on integrated circuit (IC) chips

Method for an efficient modeling of the impact of device-level self-heating on electromigration limited current specifications