Inventor

WENDEL DIETER

DE61 patents

⚠️ This page may combine multiple inventors who share the name “WENDEL DIETER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WENDEL DIETER

IBM

Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talk

System and method testing computer memories

Method for handling 32 bit results for an out-of-order processor with a 64 bit architecture

Read/write alignment scheme for port reduction of multi-port SRAM cells

Storage cell with integrated soft error detection and correction

Circular buffer with n sequential real and virtual entry positions for selectively inhibiting n adjacent entry positions including the virtual entry positions

High performance shared cache

Selectively degrading current resistance of field effect transistor devices

Apparatus and method for hardening latches in SOI CMOS devices

Method and system for pipeline reduction

Method to reduce leakage of a SRAM-array

Unified local clock buffer structures

Methods and apparatus for operating master-slave latches

Latching dynamic logic structure, and integrated circuit including same

Hierarchical priority filter with integrated serialization for determining the entry with the highest priority in a buffer memory

Current-mode sense amplifier

Structure for reducing pre-charge voltage for static random-access memory arrays

Ball grid array configuration for reliable testing

Method and an integrated circuit for performing a test

Scan chain disable function for power saving

Low skew, power efficient local clock signal generation system

SOI array sense and write margin qualification

Signal distribution in integrated circuit using optical through silicon via

Methods for modeling latch transparency

Multiport memory cell having a reduced number of write wordlines

Static wordline redundancy memory device

Microelectronic device with a memory element utilizing stacked vertical devices

Buried conductive layer supplying digital circuits

Current-mode sense amplifier

Structure for reducing pre-charge voltage for static random-access memory arrays

Method of ensuring electrical contact between test probes and chip pads through the use of vibration and nondestructive deformation

Selectively degrading current resistance of field effect transistor devices

Rename finish conflict detection and recovery

Static logic compatible multiport latch

Restore function for memory cells using negative bitline-selection

Method and system to improve usage of an instruction window buffer in multi-processor, parallel processing environments

Method for verifying cross-sections

Selectively degrading current resistance of field effect transistor devices

Signal distribution in integrated circuit using optical through silicon via

Apparatus and method for hardening latches in SOI CMOS devices

Scan chain disable function for power saving

Pulse-width limited chip clock design

Memory array with multiple read ports

Multiple port memory apparatus

Integrated circuit with vertical structures on nodes of a grid

Microelectronic device utilizing stacked vertical devices

Current-mode sense amplifier

Structure for reducing pre-charge voltage for static random-access memory arrays

GLOBALFOUNDRIES INC

Ball grid array configuration for reliable testing

GEMMEKE TOBIAS

Permute unit and method to operate a permute unit