Inventor

LEVENTIS PAUL

CA46 patents

⚠️ This page may combine multiple inventors who share the name “LEVENTIS PAUL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEVENTIS PAUL

ALTERA CORP

PLD architecture for flexible placement of IP function blocks

Redundancy structures and methods in a programmable logic device

Distributed random access memory in a programmable logic device

Apparatus and methods for optimizing the performance of programmable logic devices

Multiplexing device including a hardwired multiplexer in a programmable logic device

Versatile logic element and logic array block

Versatile logic element and logic array block

Routing architecture for a programmable logic device

Programmable logic device with redundant circuitry

Simultaneous switching noise analysis using superposition techniques

Distributed memory in field-programmable gate array integrated circuit devices

Distributed memory in field-programmable gate array integrated circuit devices

Data compression and decompression techniques for programmable circuits

Flexible I/O routing resources

Power-driven timing analysis and placement for programmable logic

Redundancy structures and methods in a programmable logic device

Routing architecture for a programmable logic device

Use of dangling partial lines for interfacing in a PLD

PLD architecture for flexible placement of IP function blocks

Versatile logic element and logic array block

Methods for designing PLD architectures for flexible placement of IP function blocks

PLD architecture for flexible placement of IP function blocks

PLD architecture for flexible placement of IP function blocks

Method and apparatus for enhancing signal routability

Routing architecture with high speed I/O bypass path

System and method for optimizing routing lines in a programmable logic device

Use of dangling partial lines for interfacing in a PLD

Versatile logic element and logic array block

Distributed random access memory in a programmable logic device

Flexible routing resources in a programmable logic device

GOOGLE LLC

Methods and systems for rendering and encoding content for online interactive gaming sessions

Memory management in gaming rendering

Resolution-based scaling of real-time interactive graphics

Resolution-based scaling of real-time interactive graphics

Memory management in gaming rendering

Resolution-based scaling of real-time interactive graphics

Methods and systems for rendering and encoding content for online interactive gaming sessions

Distributed sample-based game profiling with game metadata and metrics and gaming API platform supporting third-party content

Shadow tracking of real-time interactive simulations for complex system analysis

FENDER JOSHUA DAVID

Pessimism removal in the modeling of simultaneous switching noise

Simultaneous switching noise optimization

LEE ANDY L

PLD architecture for flexible placement of IP function blocks

PLD architecture for flexible placement of IP function blocks

LEWIS DAVID

Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage

CHAN MICHAEL

Redundancy structures and methods in a programmable logic device

KRETCHMER YARON

Power-driven timing analysis and placement for programmable logic