Inventor

CHEN XIANGDONG

US167 patents

⚠️ This page may combine multiple inventors who share the name “CHEN XIANGDONG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN XIANGDONG

IBM

Method for producing field effect device that includes epitaxially growing SiGe source/drain regions laterally from a silicon body

High mobility heterojunction complementary field effect transistors and methods thereof

Channel MOSFET with strained silicon channel on strained SiGe

MOSFET structure with high mechanical stress in the channel

Semiconductor device structure having enhanced performance FET device

Dual stress liner

Vertical MOSFET with dual work function materials

Dynamic threshold voltage MOSFET on SOI

Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors

Work function engineering for eDRAM MOSFETs

Structure and method to integrate dual silicide with dual stress liner to improve CMOS performance

Heterojunction tunneling field effect transistors, and methods for fabricating the same

Electronically programmable fuse having anode and link surrounded by low dielectric constant material

MOSFET with laterally graded channel region and method for manufacturing same

Structure and method to optimize strain in CMOSFETs

Gate controlled floating well vertical MOSFET

Selective stress engineering for SRAM stability improvement

Structure of static random access memory with stress engineering for stability

CHEN XIANGDONG

Work function engineering for eDRAM MOSFETs

Method and structure to improve body effect and junction capacitance

Heterojunction tunneling field effect transistors, and methods for fabricating the same

Heterojunction tunneling field effect transistors, and methods for fabricating the same

Method to increase effective MOSFET width

High pressure deuterium treatment for semiconductor/high-K insulator interface

Asymmetric channel MOSFET

Method for fabricating a MOS transistor with reduced channel length variation and related structure

Asymmetric channel MOSFET

MIM capacitor having a local interconnect metal electrode and related structure

QUALCOMM INC

Metal oxide semiconductor cell device architecture with mixed diffusion break isolation trenches

Low-area low clock-power flip-flop

Standard cell architecture for reduced leakage current and improved decoupling capacitance

Grounding dummy gate in scaled layout design

High performance standard cell with continuous oxide definition and characterized leakage current

V1 and higher layers programmable ECO standard cells

SOC design with critical technology pitch alignment

KARIKALAN SAMPATH K V

Semiconductor package with integrated electromagnetic shielding

Semiconductor package with a bridge interposer

Semiconductor package with ultra-thin interposer without through-semiconductor vias

BROADCOM CORP

FinFET based one-time programmable device

Semiconductor package with a bridge interposer

Decoupling composite capacitor in a semiconductor wafer

TAIWAN SEMICONDUCTOR MFG CO LTD

Low-power flip-flop architecture with high-speed transmission gates

Semiconductor device and method of manufacturing the same

ZHAO SAM ZIQUN

Semiconductor packages with integrated heat spreaders

Semiconductor package with integrated selectively conductive film interposer

UNIV TEXAS

Submicron MOSFET having asymmetric channel profile

FORD GLOBAL TECH LLC

Injection spray pattern for direct injection spark ignition engines

CAI JIN

Structure and method for Vt tuning and short channel control with high k/metal gate MOSFETs

KHAN REZAUR RAHMAN

Semiconductor interposer having a cavity for intra-interposer die

HUI FRANK

Programmable memory cell with shiftable threshold voltage transistor