Inventor
CHOI JEONG Y
US18 patents
⚠️ This page may combine multiple inventors who share the name “CHOI JEONG Y”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEGRATED DEVICE TECH
8 patentsUS5888861AMar 30, 1999
Method of manufacturing a BiCMOS integrated circuit fully integrated within a CMOS process flow
INTEGRATED DEVICE TECH61 citations95
US6191460B1Feb 20, 2001
Identical gate conductivity type static random access memory cell
INTEGRATED DEVICE TECH28 citations92
US6069054AMay 30, 2000
Method for forming isolation regions subsequent to gate formation and structure thereof
INTEGRATED DEVICE TECH44 citations92
US5679588AOct 21, 1997
Method for fabricating P-wells and N-wells having optimized field and active regions
INTEGRATED DEVICE TECH32 citations92
US5128731AJul 7, 1992
Static random access memory cell using a P/N-MOS transistors
INTEGRATED DEVICE TECH22 citations92
US6258693B1Jul 10, 2001
Ion implantation for scalability of isolation in an integrated circuit
INTEGRATED DEVICE TECH16 citations83
US5393677AFeb 28, 1995
Method of optimizing wells for PMOS and bipolar to yield an improved BICMOS process
INTEGRATED DEVICE TECH19 citations73
US5926704AJul 20, 1999
Efficient method for fabricating P-wells and N-wells
INTEGRATED DEVICE TECH1 citations52
CADENCE DESIGN SYSTEMS INC
4 patentsUS7219045B1May 15, 2007
Hot-carrier reliability design rule checker
CADENCE DESIGN SYSTEMS INC37 citations94
US7835890B2Nov 16, 2010
Hot carrier circuit reliability simulation
CADENCE DESIGN SYSTEMS INC13 citations92
US7567891B1Jul 28, 2009
Hot-carrier device degradation modeling and extraction methodologies
CADENCE DESIGN SYSTEMS INC48 citations92
US7292968B2Nov 6, 2007
Hot carrier circuit reliability simulation
CADENCE DESIGN SYSTEMS INC28 citations92