Inventor

OZGUNER TOLGA

US34 patents

⚠️ This page may combine multiple inventors who share the name “OZGUNER TOLGA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

OZGUNER TOLGA

IBM

Chip to chip interface for interconnecting chips

Method and apparatus for implementing frame header alterations using byte-wise arithmetic logic units

Method and apparatus for implementing frame header alterations

Method and apparatus for implementing alterations on multiple concurrent frames

Method and apparatus for implementing multiple configurable sub-busses of a point-to-point bus

Memory command and address conversion between an XDR interface and a double data rate interface

Memory controller operating in a system with a variable system clock

Method and apparatus for implementing chip-to-chip interconnect bus initialization

Managing write-to-read turnarounds in an early read after write memory system

Reuse of functional data buffers for pattern buffers in XDR DRAM

Memory controller operating in a system with a variable system clock

Methods and apparatus for memory calibration

Reuse of functional data buffers for pattern buffers in XDR DRAM

Method, apparatus, and computer program product for implementing pointer and stake model for frame alteration code in a network processor

Implementing conditional packet alterations based on transmit port

Managing write-to-read turnarounds in an early read after write memory system

Implementing conditional packet alterations based on transmit port

Method and apparatus for managing write-to-read turnarounds in an early read after write memory system

Optimizing data bandwidth across a variable asynchronous clock domain

MICROSOFT TECHNOLOGY LICENSING LLC

No miss cache structure for real-time image transformations with data compression

No miss cache structure for real-time image transformations with multiple LSR processing engines

Selective application of reprojection processing on layer sub-regions for optimizing late stage reprojection power

Post-rendering image transformation using parallel image transformation pipelines

No miss cache structure for real-time image transformations with multiple LSR processing engines

No miss cache structure for real-time image transformations

Interrupt controller

Methods and systems for multistage post-rendering image transformation

No miss cache structure for real-time image transformations with data compression

Reducing negative effects of insufficient data throughput for real-time processing

Reducing negative effects of insufficient data throughput for real-time processing

Selectively applying reprojection processing to multi-layer scenes for optimizing late stage reprojection power

BELLOWS MARK DAVID

Memory controller to utilize DRAM write buffers

IMMING KERRY CHRISTOPHER

Implementing pointer and stake model for frame alteration code in a network processor

FAGERNESS GERALD G

Methods and apparatus for indexing memory of a network processor