Inventor
RAGHAVAN VIJAY
US61 patents
⚠️ This page may combine multiple inventors who share the name “RAGHAVAN VIJAY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
RAGHAVAN VIJAY
13 patentsUS8726233B1May 13, 2014
System and method of using an active link in a state programming environment to locate an element
RAGHAVAN VIJAY34 citations94
US8234630B2Jul 31, 2012
Calling an entity of a graphical model with a non-graphical entity and calling a non-graphical entity of a graphical model with a graphical entity
RAGHAVAN VIJAY27 citations92
US8436726B2May 7, 2013
Stage evaluation of a state machine
RAGHAVAN VIJAY8 citations84
US8201140B2Jun 12, 2012
System and method for creating and using graphical object instances in a statechart environment
RAGHAVAN VIJAY7 citations83
US8141060B2Mar 20, 2012
Calling an entity of a graphical model with a non-graphical entity and calling a non-graphical entity of a graphical model with a graphical entity
RAGHAVAN VIJAY10 citations83
US8260597B1Sep 4, 2012
Accessing time driven environment data stores from a state driven environment
RAGHAVAN VIJAY7 citations82
US8464188B1Jun 11, 2013
Multi-rate hierarchical state diagrams
RAGHAVAN VIJAY3 citations63
US8418097B2Apr 9, 2013
Multi-rate hierarchical state diagrams
RAGHAVAN VIJAY4 citations63
US8200807B2Jun 12, 2012
Non-blocking local events in a state-diagramming environment
RAGHAVAN VIJAY3 citations63
US8700374B1Apr 15, 2014
System and method of using an active link in a state programming environment to locate an element in a graphical programming environment
RAGHAVAN VIJAY0 citations52
US8504336B1Aug 6, 2013
Hierarchically scoped resettable variables in graphical modeling environments
RAGHAVAN VIJAY0 citations52
US8214783B2Jul 3, 2012
Stage evaluation of a state machine
RAGHAVAN VIJAY0 citations52
US8881097B2Nov 4, 2014
System and method for creating and using graphical object instances in a statechart environment
RAGHAVAN VIJAY1 citations51
MATHWORKS INC
12 patentsUS8046751B1Oct 25, 2011
Structuring unstructured regions in a control flow graph
MATHWORKS INC49 citations94
US7500209B2Mar 3, 2009
Stage evaluation of a state machine
MATHWORKS INC13 citations93
US7840913B1Nov 23, 2010
Restricting state diagrams with a set of predefined requirements to restrict a state diagram to a state diagram of a moore or mealy machine
MATHWORKS INC29 citations92
US7503027B1Mar 10, 2009
Hardware description language code generation from a state diagram
MATHWORKS INC42 citations92
US7500220B1Mar 3, 2009
Shared code management
MATHWORKS INC19 citations90
US7966162B1Jun 21, 2011
Hierarchically scoped resettable variables in graphical modeling environments
MATHWORKS INC7 citations84
US7945886B2May 17, 2011
Stage evaluation of a state machine
MATHWORKS INC10 citations84
US7900191B1Mar 1, 2011
System and method of using an active link in a state programming environment to locate an element in a graphical programming environment
MATHWORKS INC8 citations84
US7877245B1Jan 25, 2011
Graphical functions
MATHWORKS INC3 citations63
US8965742B1Feb 24, 2015
Hierarchically scoped resettable variables in graphical modeling environments
MATHWORKS INC0 citations52
US7844943B2Nov 30, 2010
System and method for providing indicators of textual items having intrinsic executable computational meaning within a graphical language environment
MATHWORKS INC0 citations52
US9588744B2Mar 7, 2017
Renaming instances of an entity in a coding environment
MATHWORKS INC1 citations51
CYPRESS SEMICONDUCTOR CORP
8 patentsUS8040175B2Oct 18, 2011
Supply regulated charge pump system
CYPRESS SEMICONDUCTOR CORP21 citations93
US9449655B1Sep 20, 2016
Low standby power with fast turn on for non-volatile memory devices
CYPRESS SEMICONDUCTOR CORP20 citations91
US7701281B1Apr 20, 2010
Flyback capacitor level shifter feedback regulation for negative pumps
CYPRESS SEMICONDUCTOR CORP5 citations74
US9595332B2Mar 14, 2017
High speed, high voltage tolerant circuits in flash path
CYPRESS SEMICONDUCTOR CORP5 citations73
US10032517B2Jul 24, 2018
Memory architecture having two independently controlled voltage pumps
CYPRESS SEMICONDUCTOR CORP2 citations71
US9438240B1Sep 6, 2016
Biasing circuit for level shifter with isolation
CYPRESS SEMICONDUCTOR CORP5 citations71
US9704585B2Jul 11, 2017
High voltage architecture for non-volatile memory
CYPRESS SEMICONDUCTOR CORP3 citations68
US10062423B2Aug 28, 2018
Low standby power with fast turn on for non-volatile memory devices
CYPRESS SEMICONDUCTOR CORP0 citations51
Infineon Technologies LLC
3 patentsUS12300342B2May 13, 2025
System and method for testing a non-volatile memory
Infineon Technologies LLC0 citations62
US12045714B2Jul 23, 2024
In-memory computing architecture and methods for performing MAC operations
Infineon Technologies LLC0 citations60
US11586896B2Feb 21, 2023
In-memory computing architecture and methods for performing MAC operations
Infineon Technologies LLC1 citations60
Longitude Flash Memory Solutions Ltd
3 patentsUS12014800B2Jun 18, 2024
Low standby power with fast turn on method for non-volatile memory devices
Longitude Flash Memory Solutions Ltd0 citations61
US11581029B2Feb 14, 2023
Low standby power with fast turn on method for non-volatile memory devices
Longitude Flash Memory Solutions Ltd0 citations61
US10998019B2May 4, 2021
Low standby power with fast turn on method for non-volatile memory devices
Longitude Flash Memory Solutions Ltd0 citations61
HIROSE RYAN T
2 patentsCISCO TECH INC
1 patentAVADHANULA SRINATH
1 patentZHAO ZHIHONG
1 patentMANI RAMAMURTHY
1 patentBIENKOWSKI JOSEPH
1 patentVMWARE INC
1 patentZONTE CRISTINEL
1 patentFENG YANG
1 patentTORGERSON JAY RYAN
1 patentShowing the top 50 of 61 patents by PatentIndex Score.