Inventor

FEISTE KURT A

US24 patents

⚠️ This page may combine multiple inventors who share the name “FEISTE KURT A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

FEISTE KURT A

IBM

Information handling system with real and virtual load/store instruction issue queue

Redistribution of architected states for a processor register file

Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition

Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline

Instruction chaining

Method and system for determining multiple unused registers in a processor

Processor providing intelligent management of values buffered in overlaid architected and non-architected register files

Instruction dispatch routing

Parallel dispatching of multi-operation instructions in a multi-slice computer processor

Parallel dispatching of multi-operation instructions in a multi-slice computer processor

Routing instruction results to a register block of a subdivided register file based on register block utilization rate

Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor

Operation of a multi-slice processor implementing datapath steering

Operation of a multi-slice processor implementing datapath steering

Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core

Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core

Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor using null internal operations (IOPs)

Parallel slice processor shadowing states of hardware threads across execution slices

Parallel slice processor shadowing states of hardware threads across execution slices

Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port

Operation of a multi-slice processor implementing load-hit-store handling

Operation of a multi-slice processor with history buffers storing transaction memory state information

ABERNATHY CHRISTOPHER M

Issue unit for placing a processor into a gradual slow mode of operation