Inventor

CAMPBELL BRIAN J

US47 patents

⚠️ This page may combine multiple inventors who share the name “CAMPBELL BRIAN J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CAMPBELL BRIAN J

APPLE INC

Low latency, power-down safe level shifter

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Level shifter with embedded logic and low minimum voltage

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

L1 cache flush when processor is entering low power mode

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Leakage and NBTI reduction technique for memory

Clock gater with test features and low setup time

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Low latency, power-down safe level shifter

Level shifter with embedded logic and low minimum voltage

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Fast hit override

BROADCOM CORP

Dynamic to static converter with noise suppression

Dynamic scan circuitry for B-phase

Circuit for lines with multiple drivers

Scan interface

Dynamic scan circuitry for B-phase

Conditional clock buffer circuit

Conditional clock buffer circuit

High-fanin static multiplexer

Monotonic leakage-tolerant logic circuits

Dynamic to static converter with noise suppression

Dynamic scan circuitry for A-phase

Circuit for lines with multiple drivers

High-speed bank select multiplexer latch

High-speed bank select multiplexer latch

CAMPBELL BRIAN J

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Performing stuck-at testing using multiple isolation circuits

Clock gater with test features and low setup time

Level shifter with embedded logic and low minimum voltage

Leakage and NBTI reduction technique for memory

Cache optimizations using multiple threshold voltage transistors

Animated novelty device

Fast hit override

Leakage and NBTI reduction technique for memory

Animated novelty device

PA SEMI INC

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage

Recovering bit lines in a memory array after stopped clock operation

ABBOTT LAB

Ultra violet radiation lignin protected pesticidal compositions

KELLER JAMES B

L1 flush mechanism to flush cache for power down and handle coherence during flush and/or after power down