Inventor

CAMACHO ZIGMUND R

SG59 patents

⚠️ This page may combine multiple inventors who share the name “CAMACHO ZIGMUND R”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CAMACHO ZIGMUND R

CAMACHO ZIGMUND R

Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die

Semiconductor device and method of forming leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect

Semiconductor device and method of forming a reconfigured stackable wafer level package with vertical interconnect

Semiconductor device and method of forming EWLB package with standoff conductive layer over encapsulant bumps

Semiconductor device and method of forming wafer-level multi-row etched leadframe with base leads and embedded semiconductor die

Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumps

Semiconductor device and method of forming wafer level multi-row etched lead package

Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSP

Semiconductor device and method of forming EWLB package containing stacked semiconductor die electrically connected through conductive vias formed in encapsulant around die

Wafer level die integration and method

Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps

Semiconductor device and method of forming vertical interconnect structure between non-linear portions of conductive layers

Semiconductor device and method of forming wafer level die integration

System and apparatus for wafer level integration of components

Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device

Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection

Wirebondless wafer level package with plated bumps and interconnects

Optical semiconductor device having pre-molded leadframe with window and method therefor

Optical semiconductor device having pre-molded leadframe with window and method therefor

Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device

STATS CHIPPAC LTD

Method and apparatus for thermally enhanced semiconductor package

Leadframe design for QFN package with top terminal leads

Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device

Method of forming a wafer level package with RDL interconnection over encapsulant between bump and semiconductor die

Wirebondless wafer level package with plated bumps and interconnects

Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the same

Semiconductor device and method of forming RDL and vertical interconnect by laser direct structuring

Leadframe interposer over semiconductor die and TSV substrate for vertical electrical interconnect

Method and apparatus for a package having multiple stacked die

Semiconductor device and method of providing a thermal dissipation path through RDL and conductive via

Semiconductor package and method of forming similar structure for top and bottom bonding pads

Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof

Leadframe design for QFN package with top terminal leads

Optical semiconductor device having pre-molded leadframe with window and method therefor

Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure

Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumps

Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die

Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection

Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die

PAGAILA REZA A

Through hole vias at saw streets including protrusions or recesses for interconnection

Through hole vias at saw streets including protrusions or recesses for interconnection

Apparatus for thermally enhanced semiconductor package

Apparatus for thermally enhanced semiconductor package

BATHAN HENRY D

Semiconductor device and method of forming overlapping semiconductor die with coplanar vertical interconnect structure

Semiconductor device and method of forming leadframe with notched fingers for stacking semiconductor die

TAY LIONEL CHIEN HUI

Semiconductor device and method of forming a conductive via-in-via structure

Semiconductor device and method of providing a thermal dissipation path through RDL and conductive via

ST ASSEMBLY TEST SERVICES INC

System for semiconductor package with stacked dies

BADAKERE GURUPRASAD G

Semiconductor device and method of forming wafer level ground plane and power ring

DAHILIG FREDERICK R

Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die