Inventor
CAPARAS JOSE A
SG15 patents
⚠️ This page may combine multiple inventors who share the name “CAPARAS JOSE A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
STATS CHIPPAC LTD
7 patentsUS9443797B2Sep 13, 2016
Semiconductor device having wire studs as vertical interconnect in FO-WLP
STATS CHIPPAC LTD55 citations96
US7964450B2Jun 21, 2011
Wirebondless wafer level package with plated bumps and interconnects
STATS CHIPPAC LTD22 citations92
US10453785B2Oct 22, 2019
Semiconductor device and method of forming double-sided fan-out wafer level package
STATS CHIPPAC LTD14 citations84
US9293401B2Mar 22, 2016
Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLP-MLP)
STATS CHIPPAC LTD11 citations84
US9054083B2Jun 9, 2015
Semiconductor device and method of making TSV interconnect structures using encapsulant for structural support
STATS CHIPPAC LTD4 citations83
US9153544B2Oct 6, 2015
Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die
STATS CHIPPAC LTD3 citations63
US9142428B2Sep 22, 2015
Semiconductor device and method of forming FO-WLCSP with multiple encapsulants
STATS CHIPPAC LTD2 citations63
PAGAILA REZA A
2 patentsUS8258012B2Sep 4, 2012
Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die
PAGAILA REZA A25 citations92
US8710635B2Apr 29, 2014
Semiconductor device and method of forming discontinuous ESD protection layers between semiconductor die
PAGAILA REZA A2 citations63
SUTHIWONGSUNTHORN NATHAPONG
2 patentsUS8659162B2Feb 25, 2014
Semiconductor device having an interconnect structure with TSV using encapsulant for structural support
SUTHIWONGSUNTHORN NATHAPONG19 citations90
US8067308B2Nov 29, 2011
Semiconductor device and method of forming an interconnect structure with TSV using encapsulant for structural support
SUTHIWONGSUNTHORN NATHAPONG28 citations90
JCET SEMICONDUCTOR SHAOXING CO LTD
2 patentsUS11127668B2Sep 21, 2021
Semiconductor device and method of forming double-sided fan-out wafer level package
JCET SEMICONDUCTOR SHAOXING CO LTD0 citations60
US10622293B2Apr 14, 2020
Semiconductor device and method for forming a low profile embedded wafer level ball grid array molded laser package (EWLB-MLP)
JCET SEMICONDUCTOR SHAOXING CO LTD0 citations51