Inventor · disambiguated record
Paul E. Schardt
Also filed as: SCHARDT PAUL · SCHARDT PAUL E · SCHARDT PAUL EMERY
151 granted patents·18 pending applications·1,244 citations·filing 2004–2022
99Inventor score
Top patents by PatentIndex Score
169 records- 0199US11068318B2Dynamic thread status retrieval using inter-thread communicationIBM·Filed 2019·Granted Jul 20, 2021·143 cites·11 claims
- 0299US7719532B2Efficient and flexible data organization for acceleration data structure nodesIBM·Filed 2007·Granted May 18, 2010·137 cites·20 claims
- 0396US8261025B2Software pipelining on a network on chipMEJDRICH ERIC O·Filed 2007·Granted Sep 4, 2012·45 cites·15 claims
- 0496US8020168B2Dynamic virtual software pipelining on a network on chipIBM·Filed 2008·Granted Sep 13, 2011·65 cites·20 claims
- 0596US7991978B2Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processorIBM·Filed 2008·Granted Aug 2, 2011·60 cites·22 claims
- 0696US7973804B2Image processing with highly threaded texture fragment generationIBM·Filed 2008·Granted Jul 5, 2011·51 cites·25 claims
- 0795US8661455B2Performance event triggering through direct interthread communication on a network on chipMEJDRICH ERIC O·Filed 2009·Granted Feb 25, 2014·45 cites·14 claims
- 0895US7958340B2Monitoring software pipeline performance on a network on chipIBM·Filed 2008·Granted Jun 7, 2011·43 cites·16 claims
- 0993US8140832B2Single step mode in a software pipeline within a highly threaded network on a chip microprocessorMEJDRICH ERIC O·Filed 2009·Granted Mar 20, 2012·34 cites·16 claims
- 1092US9600618B2Implementing system irritator accelerator FPGA unit (AFU) residing behind a coherent attached processors interface (CAPI) unitIBM·Filed 2015·Granted Mar 21, 2017·12 cites·9 claims
- 1192US9582277B2Indirect instruction predicationIBM·Filed 2016·Granted Feb 28, 2017·6 cites·5 claims
- 1292US9292290B2Instruction set architecture with opcode lookup using memory attributeIBM·Filed 2013·Granted Mar 22, 2016·13 cites·11 claims
- 1392US9147078B2Instruction set architecture with secure clear instructions for protecting processing unit architected state informationIBM·Filed 2013·Granted Sep 29, 2015·15 cites·12 claims
- 1491US8751830B2Memory address translation-based data encryption/compressionMUFF ADAM J·Filed 2012·Granted Jun 10, 2014·16 cites·22 claims
- 1591US8405670B2Rolling texture context data structure for maintaining texture data in a multithreaded image processing pipelineMEJDRICH ERIC O·Filed 2010·Granted Mar 26, 2013·14 cites·25 claims
- 1691US8350846B2Updating ray traced acceleration data structures between frames based on changing perspectiveIBM·Filed 2009·Granted Jan 8, 2013·25 cites·25 claims
- 1790US10892944B2Selecting and using a cloud-based hardware acceleratorIBM·Filed 2018·Granted Jan 12, 2021·6 cites·16 claims
- 1890US8593459B2Tree insertion depth adjustment based on view frustum and distance cullingMEJDRICH ERIC OLIVER·Filed 2012·Granted Nov 26, 2013·11 cites·25 claims
- 1989US8898396B2Software pipelining on a network on chipMEJDRICH ERIC O·Filed 2012·Granted Nov 25, 2014·10 cites·15 claims
- 2089US8619078B2Parallelized ray tracingMEJDRICH ERIC O·Filed 2010·Granted Dec 31, 2013·12 cites·20 claims
- 2189US8587596B2Multithreaded software rendering pipeline with dynamic performance-based reallocation of raster threadsMEJDRICH ERIC O·Filed 2010·Granted Nov 19, 2013·12 cites·23 claims
- 2288US9710274B2Extensible execution unit interface architecture with multiple decode logic and multiple execution unitsIBM·Filed 2016·Granted Jul 18, 2017·4 cites·16 claims
- 2388US9619234B2Indirect instruction predicationIBM·Filed 2016·Granted Apr 11, 2017·4 cites·20 claims
- 2488US9256574B2Dynamic thread status retrieval using inter-thread communicationIBM·Filed 2013·Granted Feb 9, 2016·7 cites·11 claims
- 2588US8990833B2Indirect inter-thread communication using a shared pool of inboxesKUESEL JAMIE R·Filed 2011·Granted Mar 24, 2015·12 cites·22 claims
- 2687US9354887B2Instruction buffer bypass of target instruction in response to partial flushMEJDRICH ERIC O·Filed 2010·Granted May 31, 2016·11 cites·24 claims
- 2787US9183399B2Instruction set architecture with secure clear instructions for protecting processing unit architected state informationIBM·Filed 2013·Granted Nov 10, 2015·8 cites·24 claims
- 2886US9652239B2Instruction set architecture with opcode lookup using memory attributeIBM·Filed 2016·Granted May 16, 2017·3 cites·12 claims
- 2986US9652238B2Instruction set architecture with opcode lookup using memory attributeIBM·Filed 2016·Granted May 16, 2017·3 cites·20 claims
- 3086US9594557B2Floating point execution unit for calculating packed sum of absolute differencesIBM·Filed 2016·Granted Mar 14, 2017·3 cites·18 claims
- 3186US9594562B2Extensible execution unit interface architecture with multiple decode logic and multiple execution unitsIBM·Filed 2016·Granted Mar 14, 2017·3 cites·20 claims
- 3286US9594556B2Floating point execution unit for calculating packed sum of absolute differencesIBM·Filed 2016·Granted Mar 14, 2017·3 cites·20 claims
- 3386US9542184B2Local instruction loop buffer utilizing execution unit register fileIBM·Filed 2016·Granted Jan 10, 2017·3 cites·15 claims
- 3486US9501279B2Local instruction loop buffer utilizing execution unit register fileIBM·Filed 2016·Granted Nov 22, 2016·3 cites·9 claims
- 3586US9317291B2Local instruction loop buffer utilizing execution unit register fileIBM·Filed 2013·Granted Apr 19, 2016·6 cites·8 claims
- 3686US8214845B2Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message dataHOOVER RUSSELL D·Filed 2008·Granted Jul 3, 2012·14 cites·18 claims
- 3786US8018466B2Graphics rendering on a network on chipIBM·Filed 2008·Granted Sep 13, 2011·15 cites·20 claims
- 3885US9405536B2Floating point execution unit for calculating packed sum of absolute differencesIBM·Filed 2015·Granted Aug 2, 2016·3 cites·4 claims
- 3985US9256573B2Dynamic thread status retrieval using inter-thread communicationIBM·Filed 2013·Granted Feb 9, 2016·5 cites·18 claims
- 4085US8248422B2Efficient texture processing of pixel groups with SIMD execution unitMEJDRICH ERIC OLIVER·Filed 2008·Granted Aug 21, 2012·15 cites·19 claims
- 4184US9329870B2Extensible execution unit interface architecture with multiple decode logic and multiple execution unitsIBM·Filed 2013·Granted May 3, 2016·5 cites·10 claims
- 4284US9317294B2Concurrent multiple instruction issue of non-pipelined instructions using non-pipelined operation resources in another processing coreIBM·Filed 2012·Granted Apr 19, 2016·6 cites·22 claims
- 4384US9032191B2Virtualization support for branch prediction logic enable / disable at hypervisor and guest operating system levelsMUFF ADAM J·Filed 2012·Granted May 12, 2015·8 cites·25 claims
- 4484US8954755B2Memory address translation-based data encryption with integrated encryption engineMUFF ADAM J·Filed 2012·Granted Feb 10, 2015·7 cites·25 claims
- 4584US8514232B2Propagating shared state changes to multiple threads within a multithreaded processing environmentMEJDRICH ERIC O·Filed 2010·Granted Aug 20, 2013·8 cites·25 claims
- 4683US9607120B2Implementing system irritator accelerator FPGA unit (AFU) residing behind a coherent attached processors interface (CAPI) unitIBM·Filed 2014·Granted Mar 28, 2017·8 cites·11 claims
- 4783US9507599B2Instruction set architecture with extensible register addressingGLOBALFOUNDRIES INC·Filed 2013·Granted Nov 29, 2016·6 cites·23 claims
- 4883US8776035B2Providing performance tuned versions of compiled code to a CPU in a system of heterogeneous coresIBM·Filed 2012·Granted Jul 8, 2014·6 cites·4 claims
- 4983US8719455B2DMA-based acceleration of command push buffer between host and target devicesMEJDRICH ERIC O·Filed 2010·Granted May 6, 2014·7 cites·23 claims
- 5082US9239791B2Cache swizzle with inline transpositionIBM·Filed 2013·Granted Jan 19, 2016·5 cites·11 claims
Showing the top 50 of 169 patent records by PatentIndex Score.
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