Inventor · disambiguated record
Michael Billeci
Also filed as: BILLECI MICHAEL
24 granted patents·114 citations·filing 2003–2016
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
24 records- 0194US7805634B2Error accumulation register, error accumulation method, and error accumulation systemIBM·Filed 2006·Granted Sep 28, 2010·47 cites·5 claims
- 0286US9507602B2Sharing program interrupt logic in a multithreaded processorIBM·Filed 2016·Granted Nov 29, 2016·4 cites·1 claims
- 0378US7111196B2System and method for providing processor recovery in a multi-core systemIBM·Filed 2003·Granted Sep 19, 2006·27 cites·13 claims
- 0476US9720764B2Uncorrectable memory errors in pipelined CPUsIBM·Filed 2015·Granted Aug 1, 2017·2 cites·20 claims
- 0575US8683180B2Intermediate register mapperBARRICK BRIAN D·Filed 2009·Granted Mar 25, 2014·8 cites·21 claims
- 0671US8453124B2Collecting computer processor instrumentation dataALEXANDER GREGORY W·Filed 2009·Granted May 28, 2013·5 cites·20 claims
- 0767US7278063B2Method and system for performing a hardware traceIBM·Filed 2003·Granted Oct 2, 2007·10 cites·16 claims
- 0866US8209668B2Method and system for measuring the performance of a computer system on a per logical partition basisBARTIK JANE H·Filed 2006·Granted Jun 26, 2012·3 cites·20 claims
- 0959US7971034B2Reduced overhead address mode change management in a pipelined, recycling microprocessorIBM·Filed 2008·Granted Jun 28, 2011·1 cites·1 claims
- 1059US7480833B2Method and system for performing a hardware traceIBM·Filed 2007·Granted Jan 20, 2009·3 cites·2 claims
- 1158US9665376B2Sharing program interrupt logic in a multithreaded processorIBM·Filed 2014·Granted May 30, 2017·0 cites·20 claims
- 1257US8201067B2Processor error checking for instruction dataBUSABA FADI Y·Filed 2008·Granted Jun 12, 2012·1 cites·18 claims
- 1356US9619237B2Speculative branch handling for transaction abortIBM·Filed 2016·Granted Apr 11, 2017·0 cites·1 claims
- 1455US9792124B2Speculative branch handling for transaction abortIBM·Filed 2015·Granted Oct 17, 2017·0 cites·20 claims
- 1555US9454377B2Speculative branch handling for transaction abortIBM·Filed 2016·Granted Sep 27, 2016·0 cites·1 claims
- 1653US7889569B2System, method and storage medium for controlling asynchronous updates to a registerIBM·Filed 2008·Granted Feb 15, 2011·0 cites·1 claims
- 1751US7380077B2System, method and storage medium for controlling asynchronous updates to a registerIBM·Filed 2007·Granted May 27, 2008·0 cites·5 claims
- 1850US9323640B2Method and system for measuring the performance of a computer system on a per logical partition basisBARTIK JANE H·Filed 2012·Granted Apr 26, 2016·0 cites·20 claims
- 1950US7082550B2Method and apparatus for mirroring units within a processorIBM·Filed 2003·Granted Jul 25, 2006·1 cites·12 claims
- 2049US8516228B2Supporting partial recycle in a pipelined microprocessorALEXANDER KHARY J·Filed 2008·Granted Aug 20, 2013·0 cites·16 claims
- 2149US7146520B2Method and apparatus for controlling clocks in a processor with mirrored unitsIBM·Filed 2003·Granted Dec 5, 2006·2 cites·9 claims
- 2248US7814374B2System and method for the capture and preservation of intermediate error state dataIBM·Filed 2007·Granted Oct 12, 2010·0 cites·14 claims
- 2347US7225305B2System, method and storage medium for controlling asynchronous updates to a registerIBM·Filed 2004·Granted May 29, 2007·0 cites·10 claims
- 2443US9075600B2Program status word dependency handling in an out of order microprocessor designALEXANDER GREGORY W·Filed 2010·Granted Jul 7, 2015·0 cites·18 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →