Inventor

WANG SHIANG-BAU

TW81 patents

⚠️ This page may combine multiple inventors who share the name “WANG SHIANG-BAU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

WANG SHIANG-BAU

TAIWAN SEMICONDUCTOR MFG CO LTD

Metal gate structure cutting process

Partial directional etch method and resulting structures

Method of forming metal gate to mitigate antenna defect

Integrated circuit having a contact etch stop layer

Method and system for diagnosing a semiconductor wafer

Cut-fin isolation regions and method forming same

Partial directional etch method and resulting structures

Metal gate structure cutting process

Method of manufacturing a semiconductor device

Lithography mask and method

Semiconductor structure having low-k spacer and method of manufacturing the same

Semiconductor device and method of manufacture

Semiconductor device and method of manufacture

Semiconductor device and method

Method of manufacturing a semiconductor device and a semiconductor device

Partial directional etch method and resulting structures

Semiconductor structure with patterned fin structure

Semiconductor device and method

Metal gate structure cutting process

Fin field effect transistor (FinFET) device with protection layer

Semiconductor structure and manufacturing method thereof

Semiconductor device and method

Semiconductor structure and manufacturing method thereof

TAIWAN SEMICONDUCTOR MFG

Method of forming a shallow trench isolation structure

Sidewall free CESL for enlarging ILD gap-fill window

Method of dual epi process for semiconductor device

Method of dual EPI process for semiconductor device

Epitaxial process for forming semiconductor devices

Multilayer hard mask

Hard mask removal method

MOS devices with continuous contact etch stop layer

In-situ critical dimension measurement

Etching process to avoid polysilicon notching

Isolation structure profile for gap filing

Isolation structure profile for gap filing

WANG SHIANG-BAU

Isolation structure profile for gap filling

Post CMP planarization by cluster ION beam etch

Method of fabricating gate electrode using a hard mask with spacers

Post CMP planarization by cluster ion beam etch

Process for forming a metal oxide semiconductor devices

Method of fabricating integrated circuit device, including removing at least a portion of a spacer

APPLIED MATERIALS INC

Gas distribution plate electrode for a plasma reactor

Gas distribution plate electrode for a plasma receptor

Inductive antenna for a plasma reactor producing reduced fluorine dissociation

Plasma reactor with spoke antenna having a VHF mode with the spokes in phase

WISCONSIN ALUMNI RES FOUND

Method and apparatus for plasma processing with control of ion energy distribution at the substrates

CHUNG HAN-PIN

Method of dual EPI process for semiconductor device

HUANG YU-LIEN

STI structure and method of forming bottom void in same

KAO TA-WEI

Method for forming highly strained source/drain trenches

TAIWAN SEMICONDUCTOR MANFACTURING CO LTD

Epitaxial process for forming semiconductor devices