Inventor

MAGKLIS GRIGORIOS

ES39 patents

⚠️ This page may combine multiple inventors who share the name “MAGKLIS GRIGORIOS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MAGKLIS GRIGORIOS

ADVANCED RISC MACH LTD

Transactional compare-and-discard instruction

Exception handling in transactions

Transaction nesting depth testing instruction

Permitting unaborted processing of transaction after exception mask update instruction

Address translation data invalidation

Multiply-accumulation in a data processing apparatus

Testing bit values inside vector elements

Vector add-with-carry instruction

Element by vector operations in a data processing apparatus

Replicate elements instruction

Replicate partition instruction

Handling load-exclusive instructions in apparatus having support for transactional memory

Vector length querying instruction

Handling contingent and non-contingent memory access program instructions making use of disable flag

Vector processing using loops of dynamic vector length

INTEL CORP

Frequency and voltage scaling architecture

Thread migration to improve power efficiency in a parallel processing environment

Leakage power estimation

Double rounded combined floating-point multiply and add

Double rounded combined floating-point multiply and add

Meeting point thread characterization

Frequency and voltage scaling architecture

Compressing address communications between processors

Frequency and voltage scaling architecture

Combined floating point multiplier adder with intermediate rounding logic

Image signal processor with a block checking circuit

Instruction and logic for bulk register reclamation

Instruction and logic for optimization level aware branch prediction

CAI QIONG

Thread migration to improve power efficiency in a parallel processing environment

Thread migration to improve power efficiency in a parallel processing environment

UNIV ROCHESTER

Multiple clock domain microprocessor

ALBONESI DAVID

Multiple clock domain microprocessor

LOPEZ PEDRO

Replacement policy for hot code detection

SAMUDRALA SRIDHAR

Double rounded combined floating-point multiply and add

LUPON MARC

Mechanism for facilitating dynamic and efficient fusion of computing instructions in software programs

STAVROU KYRIAKOS A

Managed instruction cache prefetching

LATORRE FERNANDO

Achieving coherence between dynamically optimized code and original code

MAGKLIS GRIGORIOS

Frequency and voltage scaling architecture

MARTINEZ RAUL

Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region