Inventor

GATES STEPHEN M

US87 patents

⚠️ This page may combine multiple inventors who share the name “GATES STEPHEN M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GATES STEPHEN M

IBM

Structures and methods for integration of ultralow-k dielectrics with improved reliability

Very low effective dielectric constant interconnect structures and methods for fabricating the same

Formation of arrays of microelectronic elements

Magnetic storage medium formed of nanoparticles

Advanced manganese/manganese nitride cap/etch mask for air gap formation scheme in nanocopper low-K interconnect

Air gap semiconductor structure with selective cap bilayer

Low K and ultra low K SiCOH dielectric films and methods to form the same

Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made

Low k and ultra low k SiCOH dielectric films and methods to form the same

Very low effective dielectric constant interconnect Structures and methods for fabricating the same

Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same

Interconnect structures containing stress adjustment cap layer

Nonlithographic method to produce masks by selective reaction, articles produced, and composition for same

Reliable low-k interconnect structure with hybrid dielectric

Reliable BEOL integration process with direct CMP of porous SiCOH dielectric

Formation of arrays of microelectronic elements

Patterning layers comprised of spin-on ceramic films

SiCOH dielectric material with improved toughness and improved Si-C bonding, semiconductor device containing the same, and method to make the same

Nanoparticle structures utilizing synthetic DNA lattices

Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made

Reliable low-k interconnect structure with hybrid dielectric

Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof

Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof

Fine-pitch device lithography using a sacrificial hardmask

Low resistance metal contacts to interconnects

Method for forming semiconductor chip with graphene based devices in an interconnect structure of the chip

SiCOH film preparation using precursors with built-in porogen functionality

SiCOH dielectric material with improved toughness and improved Si-C bonding

Materials containing voids with void size controlled on the nanometer scale

SiCOH film preparation using precursors with built-in porogen functionality

Hardmask for reliability of silicon based dielectrics

Method of forming an air gap semiconductor structure with selective cap bilayer

Nonlithographic method to produce self-aligned mask, articles produced by same and compositions for same

Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modification

Patterning layers comprised of spin-on ceramic films

Magnetic-field sensor device

Nanoparticle structures utilizing synthetic DNA lattices

Selective and conformal passivation layer for 3D high-mobility channel devices

Low resistance metal contacts to interconnects

Low-loss large-grain optical waveguide for interconnecting components integrated on a glass substrate

EDELSTEIN DANIEL C

Reliable physical unclonable function for device authentication

Structure with sub-lithographic random conductors as a physical unclonable function

Method of fabricating a SiCOH dielectric material with improved toughness and improved Si-C bonding

(unassigned)

Inflatable cushioning device with self opening intake valve

Layered structure of a substrate, a dielectric layer and a single crystal layer

GATES STEPHEN M

BEOL structures incorporating active devices and mechanical strength

Materials containing voids with void size controlled on the nanometer scale

SONSUB INC

Diverless flowline connection system

DIMITRAKOPOULOS CHRISTOS D

Semiconductor chip with graphene based devices in an interconnect structure of the chip

KURSUN EREN

Non-volatile memory based reliability and availability mechanisms for a computing device