Inventor

MURALIDHAR RAMACHANDRAN

US102 patents

⚠️ This page may combine multiple inventors who share the name “MURALIDHAR RAMACHANDRAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MURALIDHAR RAMACHANDRAN

FREESCALE SEMICONDUCTOR INC

Process of forming a non-volatile memory cell including a capacitor structure

Transistor having three electrically isolated electrodes and method of formation

Integrated circuit having multiple memory types and method of formation

Memory with charge storage locations and adjacent gate structures

Method of forming nanocrystals in a memory device

Method of formation of nanocrystals on a semiconductor structure

FinFET formation with a thermal oxide spacer hard mask formed from crystalline silicon layer

Methods for programming a floating body nonvolatile memory

Transistor with independent gate structures

Method of forming a nanocluster charge storage device

Transistor with vertical dielectric structure

Semiconductor fabrication process with asymmetrical conductive spacers

Phase change memory cell with heater and method therefor

Phase change memory structures including pillars

Nanocrystal non-volatile memory cell and method therefor

Method for forming a split gate memory device

Method of forming a nanocluster charge storage device

Programming, erasing, and reading structure for an NVM cell

Method for forming a memory structure using a modified surface topography and structure thereof

Method for removing nanoclusters from selected regions

Semiconductor device with nanoclusters

Split-gate thin film storage NVM cell with reduced load-up/trap-up effects

Non-volatile nanocrystal memory and method therefor

Semiconductor device having nano-pillars and method therefor

Method for removing nanoclusters from selected regions

Method for retaining nanocluster size and electrical characteristics during processing

Process of forming an electronic device including a layer of discontinuous storage elements

Split gate memory cell using sidewall spacers

Phase change memory structures

Nanocrystal non-volatile memory cell and method therefor

Semiconductor fabrication process for integrating formation of embedded nonvolatile storage device with formation of multiple transistor device types

IBM

Extended gate sensor for pH sensing

Stressed channel FET with source/drain buffers

BEOL cross-bar array ferroelectric synapse units for domain wall movement

Encryption engine with an undetectable/tamper-proof private key in late node CMOS technology

Methods of forming FINFETs with locally thinned channels from fins having in-situ doped epitaxial cladding

Bulk finFET with super steep retrograde well

Method to optimize work function in complementary metal oxide semiconductor (CMOS) structures

Biosensors including surface resonance spectroscopy and semiconductor devices

Multi-model blending

Bulk finFET with super steep retrograde well

MOTOROLA INC

Memory device that includes passivated nanoclusters and method for manufacture

Memory device and method for using prefabricated isolated storage elements

Method of operating a semiconductor device

Memory cell and method for programming thereof

Memory device and method for manufacture

Method of operating a semiconductor device

Process for operating a semiconductor device

Method of forming a semiconductor device having a layer deposited by varying flow of reactants

EDELSTEIN DANIEL C

Reliable physical unclonable function for device authentication