Inventor

CHANG CHANG-YUN

TW86 patents

⚠️ This page may combine multiple inventors who share the name “CHANG CHANG-YUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHANG CHANG-YUN

TAIWAN SEMICONDUCTOR MFG CO LTD

Cut metal gate process for reducing transistor spacing

Metal gate structure cutting process

Isolation structure having different distances to adjacent FinFET devices

Structure and method for providing line end extensions for fin-type active regions

Etch stop layer between substrate and isolation structure

Structure and method for providing line end extensions for fin-type active regions

Memory cell layout

Structure and method for transistors with line end extension

FinFETs with different fin heights

Structure and method for providing line end extensions for fin-type active regions

Structure for fringing capacitance control

Local gate height tuning by cmp and dummy gate design

Local gate height tuning by CMP and dummy gate design

Semiconductor device having a metal gate and formation method thereof

SRAM structure and method for forming the same

Metal gate structure cutting process

Isolation structure having different distances to adjacent FinFET devices

Metal gate structure cutting process

TAIWAN SEMICONDUCTOR MFG

Integrated circuit layout design

FinFETs with multiple Fin heights

Integrated circuit layout design

Method and structure for a 1T-RAM bit cell and macro

FinFET transistor device on SOI and method of fabrication

Memory cell layout

FinFETs with multiple fin heights

FinFETs with multiple fin heights

Structure for a multiple-gate FET device and a method for its fabrication

High gate density devices and methods

Forming inter-device STI regions and intra-device STI regions using different dielectric materials

Structure and method for fabricating fin devices

Integrated circuit with multi recessed shallow trench isolation

Voids in STI regions for forming bulk FinFETs

Fully depleted SOI multiple threshold voltage application

Static noise-immune SRAM cells

Inductor energy loss reduction techniques

SHIEH MING-FENG

Cross OD FinFET patterning

High gate density devices and methods

Cross OD FinFET patterning

Method of fabrication of a semiconductor device having reduced pitch

LEE TSUNG-LIN

Integrated circuit with multi recessed shallow trench isolation

FinFETs with different fin heights

Integrated circuit structures with multiple FinFETs

YUAN FENG

STI shape near fin bottom of Si fin in bulk FinFET

Voids in STI regions for forming bulk FinFETs

Forming inter-device STI regions and intra-device STI regions using different dielectric materials

YU SHAO-MING

Structure and method for transistor with line end extension

Semiconductor device and method for making the same using semiconductor fin density design rules

LIAW JHON-JHY

Memory cell layout

CHEN HAO-YU

Fully depleted SOI multiple threshold voltage application

CHEN HUNG-MING

Integrated circuit including FINFETs and methods for forming the same