Inventor

SINGH SUNIL KUMAR

TW34 patents

⚠️ This page may combine multiple inventors who share the name “SINGH SUNIL KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SINGH SUNIL KUMAR

GLOBALFOUNDRIES INC

Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same

Filling cavities in an integrated circuit and resulting devices

Low resistance conductive contacts

Reduced capacitance interlayer structures and fabrication methods

Methods and devices for back end of line via formation

Methods of fabricating BEOL interlayer structures

Multiple-time programmable (MTP) memory device with a wrap-around control gate

Self-aligned single diffusion break for fully depleted silicon-on-insulator and method for producing the same

Interconnect structures with reduced capacitance

Metholodogy for profile control and capacitance reduction

Method to fabricate a high performance capacitor in a back end of line (BEOL)

Method to fabricate a high performance capacitor in a back end of line (BEOL)

Reducing defects and improving reliability of BEOL metal fill

Methods and devices for metal filling processes

TAIWAN SEMICONDUCTOR MFG CO LTD

Etch damage and ESL free dual damascene metal interconnect

Etch damage and ESL free dual damascene metal interconnect

Etch damage and ESL free dual damascene metal interconnect

Etch damage and ESL free dual damascene metal interconnect

Etch damage and ESL free dual damascene metal interconnect

TAIWAN SEMICONDUCTOR MFG

Air gap for interconnect application

Interconnection wires of semiconductor devices

Interconnection wires of semiconductor devices

Addition of carboxyl groups plasma during etching for interconnect reliability enhancement

GLOBALFOUNDRIES US INC

Conductive structures for contacting a top electrode of an embedded memory device and methods of making such contact structures on an IC product

Vertical memory devices

Vertical memory devices

Methods of forming a conductive contact structure to a top electrode of an embedded memory device on an IC product and a corresponding IC product

SINGH SUNIL KUMAR

Etch damage and ESL free dual damascene metal interconnect

Process for the preparation of dipeptidylpeptidase inhibitors

COUNCIL SCIENT IND RES

Method for regenerating viable and fertile citrus plants by tissue culture from explants

Formulation for improving the yield and quality of fiber in cotton plants

GLENMARK PHARMACUETICALS LTD

Process for the preparation of dipeptidylpeptidase inhibitors

REDDYS LAB INC DR

Process for the preparation of optically pure isomers of 2-(4-hydroxy phenoxy)-2-methyl-butyric acid methyl ester

IQVIA INC

Multi-agent data asset synthesis system