Inventor
RADENS CARL JOHN
US24 patents
⚠️ This page may combine multiple inventors who share the name “RADENS CARL JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
18 patentsUS7250351B2Jul 31, 2007
Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors
IBM24 citations92
US6936512B2Aug 30, 2005
Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric
IBM23 citations92
US6727540B2Apr 27, 2004
Structure and method of fabricating embedded DRAM having a vertical device array and a bordered bitline contact
IBM28 citations92
US6664161B2Dec 16, 2003
Method and structure for salicide trench capacitor plate electrode
IBM19 citations92
US6339239B1Jan 15, 2002
DRAM cell layout for node capacitance enhancement
IBM37 citations92
US6309924B1Oct 30, 2001
Method of forming self-limiting polysilicon LOCOS for DRAM cell
IBM34 citations92
US6015985AJan 18, 2000
Deep trench with enhanced sidewall surface area
IBM19 citations92
US5849638ADec 15, 1998
Deep trench with enhanced sidewall surface area
IBM24 citations92
US7129138B1Oct 31, 2006
Methods of implementing and enhanced silicon-on-insulator (SOI) box structures
IBM15 citations84
US9755030B2Sep 5, 2017
Method for reduced source and drain contact to gate stack capacitance
IBM4 citations83
US7923712B2Apr 12, 2011
Phase change memory element with a peripheral connection to a thin film electrode
IBM17 citations83
US7714452B2May 11, 2010
Structure and method for producing multiple size interconnections
IBM15 citations82
US6974991B2Dec 13, 2005
DRAM cell with buried collar and self-aligned buried strap
IBM12 citations81
US7919347B2Apr 5, 2011
Methods of fabricating P-I-N diodes, structures for P-I-N diodes and design structure for P-I-N diodes
IBM2 citations63
US6979851B2Dec 27, 2005
Structure and method of vertical transistor DRAM cell having a low leakage buried strap
IBM4 citations63
US6245651B1Jun 12, 2001
Method of simultaneously forming a line interconnect and a borderless contact to diffusion
IBM5 citations63
US7790527B2Sep 7, 2010
High-voltage silicon-on-insulator transistors and methods of manufacturing the same
IBM0 citations52
US7569450B2Aug 4, 2009
Semiconductor capacitors in hot (hybrid orientation technology) substrates
IBM0 citations42