Inventor · disambiguated record
Jeffrey A. Stuecheli
Also filed as: STUECHELI JEFFREY · STUECHELI JEFFREY A · STUECHELI JEFFREY ADAM
191 granted patents·9 pending applications·817 citations·filing 2000–2023
99Inventor score
Top patents by PatentIndex Score
200 records- 0196US9684461B1Dynamically adjusting read data return sizes based on memory interface bus utilizationIBM·Filed 2016·Granted Jun 20, 2017·20 cites·17 claims
- 0296US7469318B2System bus structure for large L2 cache array topology with different latency domainsIBM·Filed 2005·Granted Dec 23, 2008·46 cites·6 claims
- 0395US10761995B2Integrated circuit and data processing system having a configurable cache directory for an acceleratorIBM·Filed 2019·Granted Sep 1, 2020·11 cites·20 claims
- 0494US9753862B1Hybrid replacement policy in a multilevel cache memory hierarchyIBM·Filed 2016·Granted Sep 5, 2017·11 cites·13 claims
- 0594US7584329B2Data processing system and method for efficient communication utilizing an Ig coherency stateIBM·Filed 2005·Granted Sep 1, 2009·36 cites·21 claims
- 0694US7467323B2Data processing system and method for efficient storage of metadata in a system memoryIBM·Filed 2005·Granted Dec 16, 2008·33 cites·10 claims
- 0793US7805574B2Method and cache system with soft I-MRU member protection scheme during make MRU allocationIBM·Filed 2006·Granted Sep 28, 2010·31 cites·20 claims
- 0892US9727489B1Counter-based victim selection in a cache memoryIBM·Filed 2016·Granted Aug 8, 2017·8 cites·18 claims
- 0991US9891912B2Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elementsIBM·Filed 2014·Granted Feb 13, 2018·11 cites·14 claims
- 1091US9892066B1Dynamically adjusting read data return sizes based on interconnect bus utilizationIBM·Filed 2016·Granted Feb 13, 2018·7 cites·18 claims
- 1191US8930625B2Weighted history allocation predictor algorithm in a hybrid cacheDALY DAVID M·Filed 2012·Granted Jan 6, 2015·14 cites·7 claims
- 1291US7543120B2Processor and data processing system employing a variable store gather windowIBM·Filed 2007·Granted Jun 2, 2009·19 cites·8 claims
- 1390US9727488B1Counter-based victim selection in a cache memoryIBM·Filed 2016·Granted Aug 8, 2017·7 cites·18 claims
- 1490US9632942B2Expedited servicing of store operations in a data processing systemIBM·Filed 2015·Granted Apr 25, 2017·6 cites·13 claims
- 1590US8688915B2Weighted history allocation predictor algorithm in a hybrid cacheDALY DAVID M·Filed 2011·Granted Apr 1, 2014·12 cites·14 claims
- 1690US7536513B2Data processing system, cache system and method for issuing a request on an interconnect fabric without reference to a lower level cache based upon a tagged cache stateIBM·Filed 2005·Granted May 19, 2009·23 cites·18 claims
- 1789US9483424B1Peripheral component interconnect express (PCIE) pseudo-virtual channels and non-blocking writesIBM·Filed 2015·Granted Nov 1, 2016·6 cites·20 claims
- 1888US10296741B2Secure memory implementation for secure execution of virtual machinesIBM·Filed 2017·Granted May 21, 2019·4 cites·8 claims
- 1988US10216653B2Pre-transmission data reordering for a serial interfaceIBM·Filed 2017·Granted Feb 26, 2019·5 cites·19 claims
- 2088US9652399B2Expedited servicing of store operations in a data processing systemIBM·Filed 2015·Granted May 16, 2017·5 cites·6 claims
- 2188US9645937B2Expedited servicing of store operations in a data processing systemIBM·Filed 2015·Granted May 9, 2017·5 cites·13 claims
- 2288US9632943B2Expedited servicing of store operations in a data processing systemIBM·Filed 2015·Granted Apr 25, 2017·5 cites·6 claims
- 2388US9176877B2Provision of early data from a lower level cache memoryIBM·Filed 2013·Granted Nov 3, 2015·10 cites·9 claims
- 2488US7444494B2Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a history-based predictionIBM·Filed 2005·Granted Oct 28, 2008·14 cites·6 claims
- 2587US9934030B2Comparison-based sort in a reconfigurable array processor having multiple processing elements for sorting array elementsIBM·Filed 2015·Granted Apr 3, 2018·4 cites·13 claims
- 2687US9355035B2Dynamic write priority based on virtual write queue high water mark for set associative cache using cache cleaner when modified sets exceed thresholdGLOBALFOUNDRIES INC·Filed 2013·Granted May 31, 2016·8 cites·20 claims
- 2787US9058260B2Transient condition management utilizing a posted error detection processing protocolIBM·Filed 2013·Granted Jun 16, 2015·8 cites·10 claims
- 2887US8347036B2Empirically based dynamic control of transmission of victim cache lateral castoutsIBM·Filed 2009·Granted Jan 1, 2013·18 cites·44 claims
- 2986US7818511B2Reducing number of rejected snoop requests by extending time to respond to snoop requestIBM·Filed 2007·Granted Oct 19, 2010·12 cites·13 claims
- 3084US9575825B2Push instruction for pushing a message payload from a sending thread to a receiving threadIBM·Filed 2014·Granted Feb 21, 2017·6 cites·10 claims
- 3184US7380066B2Store stream prefetching in a microprocessorIBM·Filed 2005·Granted May 27, 2008·13 cites·7 claims
- 3283US12050798B2Memory migration within a multi-host data processing environmentIBM·Filed 2021·Granted Jul 30, 2024·1 cites·24 claims
- 3383US7454578B2Data processing system and method for predictively selecting a scope of broadcast of an operation utilizing a location of a memoryIBM·Filed 2005·Granted Nov 18, 2008·12 cites·20 claims
- 3483US7366851B2Processor, method, and data processing system employing a variable store gather windowIBM·Filed 2004·Granted Apr 29, 2008·25 cites·7 claims
- 3582US9940239B1Counter-based victim selection in a cache memoryIBM·Filed 2016·Granted Apr 10, 2018·4 cites·12 claims
- 3682US8139592B2Ticket-based operation trackingCLARK LEO J·Filed 2008·Granted Mar 20, 2012·11 cites·15 claims
- 3782US8122223B2Access speculation predictor with predictions based on memory region prior requestor tag informationCANTIN JASON F·Filed 2008·Granted Feb 21, 2012·11 cites·23 claims
- 3882US7734876B2Protecting ownership transfer with non-uniform protection windowsIBM·Filed 2006·Granted Jun 8, 2010·11 cites·14 claims
- 3981US11269561B2Speculative bank activate dynamic random access memory (DRAM) schedulerIBM·Filed 2020·Granted Mar 8, 2022·1 cites·20 claims
- 4081US10474816B2Secure memory implementation for secure execution of Virtual MachinesIBM·Filed 2017·Granted Nov 12, 2019·2 cites·16 claims
- 4181US9740629B2Tracking memory accesses when invalidating effective address to real address translationsIBM·Filed 2014·Granted Aug 22, 2017·5 cites·9 claims
- 4281US8352712B2Method and system for specualtively sending processor-issued store operations to a store queue with full signal assertedIBM·Filed 2004·Granted Jan 8, 2013·33 cites·28 claims
- 4381US7401189B2Pipelining D states for MRU steerage during MRU/LRU member allocationIBM·Filed 2005·Granted Jul 15, 2008·9 cites·5 claims
- 4480US10157134B2Decreasing the data handoff interval for a reserved cache line based on an early indication of a systemwide coherence responseIBM·Filed 2016·Granted Dec 18, 2018·3 cites·18 claims
- 4580US8683128B2Memory bus write prioritizationDALY DAVID M·Filed 2010·Granted Mar 25, 2014·5 cites·20 claims
- 4679US9218292B2Least-recently-used (LRU) to first-dirty-member distance-maintaining cache cleaning schedulerIBM·Filed 2013·Granted Dec 22, 2015·4 cites·11 claims
- 4779US9208091B2Coherent attached processor proxy having hybrid directoryIBM·Filed 2013·Granted Dec 8, 2015·4 cites·14 claims
- 4879US8909874B2Memory reorder queue biasing preceding high latency operationsBRITTAIN MARK A·Filed 2012·Granted Dec 9, 2014·5 cites·14 claims
- 4979US8788757B2Dynamic inclusive policy in a hybrid cache hierarchy using hit rateDALY DAVID M·Filed 2011·Granted Jul 22, 2014·5 cites·23 claims
- 5078US9361240B2Dynamic reservations in a unified request queueIBM·Filed 2013·Granted Jun 7, 2016·4 cites·19 claims
Showing the top 50 of 200 patent records by PatentIndex Score.
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