Inventor

TSENG CHIAHSUN

US53 patents

⚠️ This page may combine multiple inventors who share the name “TSENG CHIAHSUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TSENG CHIAHSUN

IBM

Self-aligned contact process enabled by low temperature

Self-aligned contact process enabled by low temperature

Self-aligned contact process enabled by low temperature

Bulk fin formation with vertical fin sidewall profile

Tone inverted directed self-assembly (DSA) fin patterning

Gate structure integration scheme for fin field effect transistors

Sidewall image transfer with a spin-on hardmask

Electrically isolated SiGe fin formation by local oxidation

Fin density control of multigate devices through sidewall image transfer processes

Trench patterning with block first sidewall image transfer

Non-merged epitaxially grown MOSFET devices

Finfet formed over dielectric

FinFET formed over dielectric

Fin density control of multigate devices through sidewall image transfer processes

Stop layer through ion implantation for etch stop

STI region for small fin pitch in FinFET devices

Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer

Contact structure employing a self-aligned gate cap

Partially isolated Fin-shaped field effect transistors

Self-aligned contact process enabled by low temperature

Fin density control of multigate devices through sidewall image transfer processes

Bulk fin formation with vertical fin sidewall profile

Methods for forming FinFETs having epitaxial Si S/D extensions with flat top surfaces on a SiGe seed layer

Non-lithographic line pattern formation

FinFETs with non-merged epitaxial S/D extensions having a SiGe seed layer on insulator

FinFETs with non-merged epitaxial S/D extensions on a seed layer and having flat top surfaces

FinFET semiconductor device having integrated SiGe fin

Densely spaced fins for semiconductor fin field effect transistors

Partially isolated fin-shaped field effect transistors

Gate structure integration scheme for fin field effect transistors

Tone inverted directed self-assembly (DSA) fin patterning

Low-K spacer for RMG finFET formation

Densely spaced fins for semiconductor fin field effect transistors

Methods for forming FinFETs with non-merged epitaxial fin extensions

Non-lithographic line pattern formation

Gate structure integration scheme for fin field effect transistors

Non-lithographic hole pattern formation

Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer

Contact structure employing a self-aligned gate cap

Non-bridging contact via structures in proximity

Non-bridging contact via structures in proximity

Self-aligned trench over fin

TSENG CHIAHSUN

Non-bridging contact via structures in proximity

Self-aligned trench over fin

Non-lithographic hole pattern formation

Non-lithographic line pattern formation

GLOBALFOUNDRIES INC

Making an efuse

Sidewall image transfer with a spin-on hardmask

FinFET with merge-free fins

GLOBAL FOUNDRIES INC

Methods of forming trench/hole type features in a layer of material of an integrated circuit product