Inventor

LEE PETER WUNG

US66 patents

⚠️ This page may combine multiple inventors who share the name “LEE PETER WUNG”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE PETER WUNG

LEE PETER WUNG

NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating same

Self-timed SLC NAND pipeline and concurrent program without verification

High speed high density nand-based 2T-NOR flash memory design

Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an array

NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array

NAND memory array with BL-hierarchical structure for concurrent all-BL, all-threshold-state program, and alternative-WL program, odd/even read and verify operations

Partial/full array/block erase for 2D/3D hierarchical NAND

Multi-task concurrent/pipeline NAND operations on all planes

VSL-based VT-compensation and analog program scheme for NAND array without CSL

NAND array architecture for multiple simultaneous program and read

NAND array architecture for multiple simutaneous program and read

Low disturbance, power-consumption, and latency in NAND read and program-verify operations

Different types of memory integrated in one chip by using a novel protocol

EEPROM-based, data-oriented combo NVM design

Universal timing waveforms sets to improve random access read and write speed of memories

Single-polycrystalline silicon electrically erasable and programmable nonvolatile memory device

Embedded NOR flash memory process with NAND cell and true logic compatible low voltage device

Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array

Row-decoder and select gate decoder structures suitable for flashed-based EEPROM operating below +/− 10v BVDS

Row-decoder and source-decoder structures suitable for erase in unit of page, sector and chip of a NOR-type flash operating below +/− 10V BVDS

High speed high density NAND-based 2T-NOR flash memory design

Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storage

Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory

NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous erase, erase-verify, program, program-verify, and read operations

APLUS FLASH TECHNOLOGY INC

Charge pump circuits

Reversed split-gate cell array

Bias condition and X-decoder circuit of flash memory array

Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operation

Non-boosting program inhibit scheme in NAND design

Approach to provide high external voltage for flash memory erase

Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash array

Bias conditions for repair, program and erase operations of non-volatile memory

Approach to provide high external voltage for flash memory erase

NAND array architecture for multiple simutaneous program and read

NAND array hiarchical BL structures for multiple-WL and all-BL simultaneous erase, erase-verify, program, program-verify, and read operations

Low-voltage page buffer to be used in NVM design

1T1b and 2T2b flash-based, data-oriented EEPROM design

NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory array

Bit line structure for a multilevel, dual-sided nonvolatile memory cell array

Multi-task concurrent/pipeline NAND operations on all planes

Shielding 2-cycle half-page read and program schemes for advanced NAND flash design

On-chip HV and LV capacitors acting as the second back-up supplies for NVSRAM auto-store operation

NOR-based BCAM/TCAM cell and array with NAND scalability

APLUS INTEGRATED CIRCUITS INC

Flash memory protection attribute status bits held in a flash memory array

Flash memory array and decoding architecture

Flash memory array and decoding architecture

Flash memory having low threshold voltage distribution

Flash memory array and decoding architecture

HSU FU-CHANG

Integrated SRAM and FLOTOX EEPROM memory device

APLUS FLASH TECH INC

2D/3D NAND memory array with bit-line hierarchical structure for multi-page concurrent SLC/MLC program and program-verify