Inventor

KATAYAMA YASUNAO

JP54 patents

⚠️ This page may combine multiple inventors who share the name “KATAYAMA YASUNAO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KATAYAMA YASUNAO

IBM

System-on-chip layout compilation

Refresh period control apparatus and method, and computer

Intelligent media memory statically mapped in unified memory architecture

Method and apparatus of burst read and pipelined dynamic random access memory having multiple pipelined stages with DRAM controller and buffers integrated on a single chip

Emulating quasi-synchronous DRAM with asynchronous DRAM

DRAM/SRAM with uniform access time using buffers, write back, address decode, read/write and refresh controllers

Reed-solomon decoder

Sense system for dynamic random access memory

Apparatus for encoding and decoding

Combinational circuit, and encoder, decoder and semiconductor device using this combinational circuit

Decoding circuit, and decoder, decoding method and semiconductor device that use the decoding circuit

Shared encoder used in error correction having multiple encoders of different maximum error correction capabilities

Signal compensation in high-speed communication

Base station power control in a mobile network

Optical interconnect device, information processing device and data transmission method

Encoding and decoding method for packet recovery

Method, hardware product, and computer program product for performing high data rate wireless transmission

Static memory cell with spaced apart conducting layers

Low overhead exclusive control for shared memory objects

Memory access for exactly-once messaging

Packet communication system, communication method and program

Base station power control in a mobile network

Coupled quantum well devices (CQWD) containing two or more direct selective contacts and methods of making same

Multiplication module, multiplicative inverse arithmetic circuit, multiplicative inverse arithmetic control method, apparatus employing multiplicative inverse arithmetic circuit, and cryptographic apparatus and error correction decoder therefor

Dynamically reconfigurable networked virtual neurons for neural network processing

Low overhead exclusive control for shared memory objects

Queue control for shared memory access

Queue control for shared memory access

Memory-side caching for shared memory objects

Information processing system, wireless communication apparatus, method and program

Information processing system, wireless communication apparatus, method and program

Transmitting device, receiving device, communication device, programs, transmission method, and receiving method for wireless communication of continuous data in the form of packets

Transmitting device, receiving device, communication device, programs, transmission method, and receiving method for wireless communication of continuous data in the form of packets

Integrity check of measured signal trace data

Integrity check of measured signal trace data

Neural network processing with von-Neumann cores

Method for controlling file request access

Method and circuit for digitally filtering a signal

Complementary logic circuit

KATAYAMA YASUNAO

Radix-8 fixed-point FFT logic circuit characterized by preservation of square root-i operation

Control and monitoring for fast millimeter-wave link using out-of-band wireless channel

Backplane structure allowing setting of equal peer-to-peer communication distance between two blades arbitrarily inserted into a plurality of fixedly arranged slots

Calculation technique for sum-product decoding method (belief propagation method) based on scaling of input log-likelihood ratio by noise variance

Packet communication system, communication method and program

Radio receiver, radio communication system, radio communication method, and program

Method for detecting and correcting phase shift between I data clock in Q data clock in quadrature modulator or quadrature demodulator

Control and monitoring for fast millimeter-wave link using out-of-band wireless channel

Radio receiver, radio communication system, radio communication method, and program

On-the-fly compensation of sampling frequency and phase offset in receiver performing ultra-high-speed wireless communication

Compensation for data deviation caused by frequency offset using timing correlation value