Inventor

KANG SEUNG HYUK

US109 patents

⚠️ This page may combine multiple inventors who share the name “KANG SEUNG HYUK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KANG SEUNG HYUK

QUALCOMM INC

Three-dimensional (3D) ferroelectric dipole metal-oxide semiconductor ferroelectric field-effect transistor (MOSFeFET) system, and related methods and systems

Hybrid synthetic antiferromagnetic layer for perpendicular magnetic tunnel junction (MTJ)

Ultrathin perpendicular pinned layer structure for magnetic tunneling junction devices

Differential spin orbit torque magnetic random access memory (SOT-MRAM) cell structure and array

High-speed, low power spin-orbit torque (SOT) assisted spin-transfer torque magnetic random access memory (STT-MRAM) bit cell array

One-time programming (OTP) magneto-resistive random access memory (MRAM) bit cells in a physically unclonable function (PUF) memory in breakdown to a memory state from a previous read operation to provide PUF operations

Magnetic tunnel junction (MTJ) devices with varied breakdown voltages in different memory arrays fabricated in a same semiconductor die to facilitate different memory applications

Self-compensation of stray field of perpendicular magnetic elements

System and method to generate a random number

High aspect ratio vertical interconnect access (via) interconnections in magnetic random access memory (MRAM) bit cells

Spin-orbit-torque magnetoresistive random access memory with voltage-controlled anisotropy

System, apparatus, and method for sense amplifiers

Embedded magnetoresistive random access memory (MRAM) integration with top contacts

Magnetic tunnel junction and method for fabricating a magnetic tunnel junction

Logic finFET high-K/conductive gate embedded multiple time programmable flash memory

MRAM integration techniques for technology scaling

MTJ structure and integration scheme

MRAM device and integration techniques compatible with logic integration

Physically unclonable function (PUF) memory employing static random access memory (SRAM) bit cells with added passive resistance to enhance transistor imbalance for improved PUF output reproducibility

Offset-cancellation sensing circuit (OCSC)-based non-volatile (NV) memory circuits

Spin-orbit torque (SOT) magnetic tunnel junction (MTJ) (SOT-MTJ) devices employing perpendicular and in-plane free layer magnetic anisotropy to facilitate perpendicular magnetic orientation switching, suitable for use in memory systems for storing data

Multiple (multi-) level cell (MLC) non-volatile (NV) memory (NVM) matrix circuits for performing matrix computations with multi-bit input vectors

Parallel write scheme utilizing spin hall effect-assisted spin transfer torque random access memory

Magneto-resistive random access memory (MRAM) employing an integrated physically unclonable function (PUF) memory

Voltage-switched magneto-resistive random access memory (MRAM) employing separate read operation circuit paths from a shared spin torque write operation circuit path

Magnetic tunnel junction (MTJ) devices with heterogeneous free layer structure, particularly suited for spin-torque-transfer (STT) magnetic random access memory (MRAM) (STT MRAM)

Back gate biasing magneto-resistive random access memory (MRAM) bit cells to reduce or avoid write operation failures caused by source degeneration

Reducing or avoiding metal deposition from etching magnetic tunnel junction (MTJ) devices, including magnetic random access memory (MRAM) devices

Magnetoresistive (MR) sensors employing dual MR devices for differential MR sensing

Electrode structure for resistive memory device

Dynamically controlling voltage for access operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations

Spin-orbit-torque magnetoresistive random access memory with voltage-controlled anisotropy

Magnetic etch stop layer for spin-transfer torque magnetoresistive random access memory magnetic tunnel junction device

De-integrated trench formation for advanced MRAM integration

Hybrid synthetic antiferromagnetic layer for perpendicular magnetic tunnel junction (MTJ)

Dual interface free layer with amorphous cap layer for perpendicular magnetic tunnel junction

MRAM integration techniques for technology scaling

Antiferromagnetically coupled spin-torque oscillator with hard perpendicular polarizer

Perpendicular magnetic tunnel junction (pMTJ) devices employing a thin pinned layer stack and providing a transitioning start to a body-centered cubic (BCC) crystalline / amorphous structure below an upper anti-parallel (AP) layer

Shared source line magnetic tunnel junction (MTJ) bit cells employing uniform MTJ connection patterns for reduced area

Switching film structure for magnetic random access memory (MRAM) cell

Magnetic tunnel junction device

Methods of integrated shielding into MTJ device for MRAM

Error correction and decoding

Dual mode sensing scheme

Offset-canceling (OC) write operation sensing circuits for sensing switching in a magneto-resistive random access memory (MRAM) bit cell in an MRAM for a write operation

QUALCOMM TECHNOLOGIES INC

Sensing voltage based on a supply voltage applied to magneto-resistive random access memory (MRAM) bit cells in an MRAM for tracking write operations to the MRAM bit cells

Metal-oxide semiconductor (MOS) transistor offset-cancelling (OC), zero-sensing (ZS) dead zone, current-latched sense amplifiers (SAs) (CLSAs) (OCZS-SAs) for sensing differential voltages

Non-volatile (NV)-content addressable memory (CAM) (NV-CAM) cells employing differential magnetic tunnel junction (MTJ) sensing for increased sense margin

QUALCOMM TECH INCORPORATED

Transistor noise tolerant, non-volatile (NV) resistance element-based static random access memory (SRAM) physically unclonable function (PUF) circuits, and related systems and methods