Inventor

GRAY JAN

US46 patents

⚠️ This page may combine multiple inventors who share the name “GRAY JAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GRAY JAN

MICROSOFT CORP

Compiler and method for avoiding unnecessary recompilation

Parallelizing sequential frameworks using transactions

Method and system for destruction of objects using multiple destructor functions in an object-oriented computer system

Method for object construction in a compiler for an object-oriented programming language

Method and system for implementing pointers to members in a compiler for an object-oriented programming language

Method for implementing pointers to members in a compiler for an object-oriented programming language

Parallelizing sequential frameworks using transactions

Code rewriting

Cache residency test instruction

Software accessible cache metadata

Metaphysically addressed cache metadata

Minimizing code duplication in an unbounded transactional memory system by using mode agnostic transactional read and write barriers

MICROSOFT TECHNOLOGY LICENSING LLC

Age-based management of instruction blocks in a processor instruction window

Decoding information about a group of instructions including a size of the group of instructions

Mapping instruction blocks based on block size

Bulk allocation of instruction blocks to a processor instruction window

Parallel decision tree processor architecture

Efficient garbage collection and exception handling in a hardware accelerated transactional memory system

Decoupled processor instruction window and operand buffer

Decoupled processor instruction window and operand buffer

Private memory regions and coherency optimization by controlling snoop traffic volume in multi-level cache hierarchy

Explicit instruction scheduler state information for a processor

GRAY JAN

Hardware accelerated transactional memory system with open nested transactions

Performing mode switching in an unbounded transactional memory (UTM) system

Cache metadata for implementing bounded transactional memory

Private memory regions and coherence optimizations

Efficient garbage collection and exception handling in a hardware accelerated transactional memory system

Cache metadata identifiers for isolation and sharing

Wait loss synchronization

Cache metadata for accelerating software transactional memory

INTEL CORP

Mechanisms to accelerate transactions using buffered stores

Performing mode switching in an unbounded transactional memory (UTM) system

Mechanisms to accelerate transactions using buffered stores

Mechanisms to accelerate transactions using buffered stores

Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode

ADL-TABATABAI ALI-REZA

Mechanisms to accelerate transactions using buffered stores

Using buffered stores or monitoring to filter redundant transactional accesses and mechanisms for mapping data to buffered metadata

Software filtering in a transactional memory system

Mechanisms to accelerate transactions using buffered stores

YAMADA KOICHI

Operating system virtual memory management for hardware transactional memory

Operating system virtual memory management for hardware transactional memory

Handling operating system (OS) transitions in an unbounded transactional memory (UTM) mode

TAILLEFER MARTIN

Debugging mechanisms in a cache-based memory isolation system

Instrumentation of hardware assisted transactional memory system

DUFFY JOHN JOSEPH

Parallelizing sequential frameworks using transactions

SHEAFFER GAD

Performing escape actions in transactions